EVAL-ADUC7026QSP Analog Devices Inc, EVAL-ADUC7026QSP Datasheet - Page 33
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EVAL-ADUC7026QSP
Manufacturer Part Number
EVAL-ADUC7026QSP
Description
KIT DEV FOR ADUC7026/7027
Manufacturer
Analog Devices Inc
Datasheet
1.EVAL-ADUC7026QSP.pdf
(92 pages)
Specifications of EVAL-ADUC7026QSP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EVAL-ADUC7026QSPZ
Manufacturer:
Analog Devices Inc
Quantity:
135
- Current page: 33 of 92
- Download datasheet (2Mb)
More information relative to the programmer’s model and the
ARM7TDMI core architecture can be found in the following
materials from ARM:
•
•
INTERRUPT LATENCY
The worst-case latency for a fast interrupt request (FIQ)
consists of the following:
•
•
•
•
DDI0029G, ARM7TDMI Technical Reference Manual
DDI-0100, ARM Architecture Reference Manual
The longest time the request can take to pass through the
synchronizer
The time for the longest instruction to complete (the
longest instruction is an LDM) that loads all the registers
including the PC
The time for the data abort entry
The time for FIQ entry
Rev. B | Page 33 of 92
At the end of this time, the ARM7TDMI executes the instruc-
tion at 0x1C (FIQ interrupt vector address). The maximum
total time is 50 processor cycles, which is just under 1.2 μs in a
system using a continuous 41.78 MHz processor clock.
The maximum interrupt request (IRQ) latency calculation is
similar, but must allow for the fact that FIQ has higher priority
and could delay entry into the IRQ handling routine for an
arbitrary length of time. This time can be reduced to 42 cycles if
the LDM command is not used. Some compilers have an option
to compile without using this command. Another option is to run
the part in thumb mode where the time is reduced to 22 cycles.
The minimum latency for FIQ or IRQ interrupts is a total of
five cycles, which consist of the shortest time the request can
take through the synchronizer, plus the time to enter the
exception mode.
Note that the ARM7TDMI always runs in ARM (32-bit) mode
when in privileged modes, for example, when executing
interrupt service routines.
ADuC7019/20/21/22/24/25/26/27/28
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