EVAL-ADUC7026QSP Analog Devices Inc, EVAL-ADUC7026QSP Datasheet - Page 13

• Manufacturer Part Number: EVAL-ADUC7026QSP
• Description: KIT DEV FOR ADUC7026/7027
• Manufacturer: Analog Devices Inc

Specifications of EVAL-ADUC7026QSP

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 6. SPI Master Mode Timing (PHASE Mode = 0)
Parameter
t
t
t
t
t
t
t
t
t
t
1
2
SL
SH
DAV
DOSU
DSU
DHD
DF
DR
SR
SF
t
t
HCLK
UCLK
depends on the clock divider or CD bits in PLLCON MMR. t
= 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider.
(POLARITY = 0)
(POLARITY = 1)
Description
SCLOCK low pulse width
SCLOCK high pulse width
Data output valid after SCLOCK edge
Data output setup before SCLOCK edge
Data input setup time before SCLOCK edge
Data input hold time after SCLOCK edge
Data output fall time
Data output rise time
SCLOCK rise time
SCLOCK fall time
SCLOCK
SCLOCK
MOSI
MISO
t
DOSU
t
DSU
MSB IN
1
1
MSB
t
DHD
t
SH
Figure 7. SPI Master Mode Timing (PHASE Mode = 0)
t
DF
HCLK
t
DAV
= t
UCLK
2
t
SL
Rev. B | Page 13 of 92
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2
CD
t
DR
.
BITS 6 TO 1
BITS 6 TO 1
Min
1 × t
2 × t
UCLK
UCLK
ADuC7019/20/21/22/24/25/26/27/28
LSB IN
t
SR
Typ
(SPIDIV + 1) × t
(SPIDIV + 1) × t
5
5
5
5
LSB
t
SF
HCLK
HCLK
Max
25
75
12.5
12.5
12.5
12.5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns