AD9510-VCO/PCB Analog Devices Inc, AD9510-VCO/PCB Datasheet - Page 31

• Manufacturer Part Number: AD9510-VCO/PCB
• Description: BOARD EVAL CLOCK DISTR 64LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD9510-VCO/PCB

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 16. P, A, B, R—Smallest Values for N
F
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
Phase Frequency Detector (PFD) and Charge Pump
The PFD takes inputs from the R counter and the N counter
(N = BP + A) and produces an output proportional to the
phase and frequency difference between them. Figure 36 is a
simplified schematic. The PFD includes a programmable delay
element that controls the width of the antibacklash pulse. This
pulse ensures that there is no dead zone in the PFD transfer
function and minimizes phase noise and reference spurs. Two
bits in Register 0Dh <1:0> control the width of the pulse.
Antibacklash Pulse
The PLL features a programmable antibacklash pulse width
that is set by the value in Register 0Dh<1:0>. The default
antibacklash pulse width is 1.3 ns (0Dh<1:0> = 00b) and
normally should not need to be changed. The antibacklash
pulse eliminates the dead zone around the phase-locked
REF
R DIVIDER
N DIVIDER
Figure 36. PFD Simplified Schematic and Timing (In Lock)
HI
HI
R
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
D1 Q1
D2 Q2
CLR1
CLR2
U1
U2
P
1
2
1
1
1
2
2
2
2
2
2
2
2
2
2
4
4
PROGRAMMABLE
ANTIBACKLASH
UP
PULSE WIDTH
DOWN
DELAY
A
X
X
X
X
X
X
0
1
2
1
X
0
1
X
0
0
1
B
1
1
3
4
5
3
3
3
3
4
5
5
5
6
6
3
3
U3
N
1
2
3
4
5
6
6
7
8
9
10
10
11
12
12
12
13
GND
V
P
CHARGE
PUMP
CP
F
10
20
30
40
50
60
60
70
80
90
100
100
110
120
120
120
130
VCO
Rev. A | Page 31 of 60
Mode
FD
FD
FD
FD
FD
FD
DM
DM
DM
DM
FD
DM
DM
FD
DM
DM
DM
condition and thereby reduces the potential for certain spurs
that could be impressed on the VCO signal.
STATUS Pin
The output multiplexer on the AD9510 allows access to
various signals and internal points on the chip at the STATUS
pin. Figure 37 shows a block diagram of the STATUS pin
section. The function of the STATUS pin is controlled by
Register 08h<5:2>.
PLL Digital Lock Detect
The STATUS pin can display two types of PLL lock detect:
digital (DLD) and analog (ALD). Whenever digital lock detect
is desired, the STATUS pin provides a CMOS level signal, which
can be active high or active low.
The digital lock detect has one of two time windows, as selected
by Register 0Dh<5>. The default (ODh<5> = 0b) requires the
signal edges on the inputs to the PFD to be coincident within
9.5 ns to set the DLD true, which then must separate by at least
15 ns to give DLD = false.
The other setting (ODh<5> = 1) makes these coincidence times
3.5 ns for DLD = true and 7 ns for DLD = false.
The DLD may be disabled by writing 1 to Register 0Dh<6>.
If the signal at REFIN goes away while DLD is true, the DLD
will not necessarily indicate loss-of-lock. See the Loss of
Reference section for more information.
Notes
P = 1, B = 1 (Bypassed)
P = 2, B = 1 (Bypassed)
P = 1, B = 3
P = 1, B = 4
P = 1, B = 5
P = 2, B = 3
P/P + 1 = 2/3, A = 0, B = 3
P/P + 1 = 2/3, A = 1, B = 3
P/P + 1 = 2/3, A = 2, B = 3
P/P + 1 = 2/3, A = 1, B = 4
P = 2, B = 5
P/P + 1 = 2/3, A = 0, B = 5
P/P + 1 = 2/3, A = 1, B = 5
P = 2, B = 6
P/P + 1 = 2/3, A = 0, B = 6
P/P + 1 = 4/5, A = 0, B = 3
P/P + 1 = 4/5, A = 1, B = 3
AD9510