AD9510-VCO/PCB Analog Devices Inc, AD9510-VCO/PCB Datasheet - Page 42

• Manufacturer Part Number: AD9510-VCO/PCB
• Description: BOARD EVAL CLOCK DISTR 64LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD9510-VCO/PCB

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

AD9510
SERIAL CONTROL PORT
The AD9510 serial control port is a flexible, synchronous, serial
communications port that allows an easy interface with many
industry-standard microcontrollers and microprocessors. The
AD9510 serial control port is compatible with most
synchronous transfer formats, including both the Motorola SPI®
and Intel® SSR® protocols. The serial control port allows
read/write access to all registers that configure the AD9510.
Single or multiple byte transfers are supported, as well as MSB
first or LSB first transfer formats. The AD9510 serial control
port can be configured for a single bidirectional I/O pin (SDIO
only) or for two unidirectional I/O pins (SDIO/SDO).
SERIAL CONTROL PORT PIN DESCRIPTIONS
SCLK (serial clock) is the serial shift clock. This pin is an input.
SCLK is used to synchronize serial control port reads and
writes. Write data bits are registered on the rising edge of this
clock, and read data bits are registered on the falling edge. This
pin is internally pulled down by a 30 kΩ resistor to ground.
SDIO (serial data input/output) is a dual-purpose pin and acts
as either an input only or as both an input/output. The AD9510
defaults to two unidirectional pins for I/O, with SDIO used as
an input, and SDO as an output. Alternatively, SDIO can be
used as a bidirectional I/O pin by writing to the SDO enable
register at 00h<7> = 1b.
SDO (serial data out) is used only in the unidirectional I/O
mode (00h<7> = 0, default) as a separate output pin for reading
back data. The AD9510 defaults to this I/O mode. Bidirectional
I/O mode (using SDIO as both input and output) may be
enabled by writing to the SDO enable register at 00h<7> = 1.
CSB (chip select bar) is an active low control that gates the read
and write cycles. When CSB is high, SDO and SDIO are in a
high impedance state. This pin is internally pulled down by a
30 kΩ resistor to ground. It should not be left NC or tied low.
See the General Operation of Serial Control Port section on the
use of the CSB in a communication cycle.
GENERAL OPERATION OF SERIAL CONTROL PORT
Framing a Communication Cycle with CSB
Each communications cycle (a write or a read operation) is
gated by the CSB line. CSB must be brought low to initiate a
communication cycle. CSB must be brought high at the
completion of a communication cycle (see Figure 52). If CSB is
not brought high at the end of each write or read cycle (on a
byte boundary), the last byte is not loaded into the register
buffer.
SCLK (PIN 18)
SDIO (PIN 19)
SDO (PIN 20)
CSB (PIN 21)
Figure 44. Serial Control Port
AD9510
CONTROL
SERIAL
PORT
Rev. A | Page 42 of 60
CSB stall high is supported in modes where three or fewer bytes
of data (plus instruction data) are transferred (W1:W0 must be
set to 00, 01, or 10, see Table 20). In these modes, CSB can
temporarily return high on any byte boundary, allowing time
for the system controller to process the next byte. CSB can go
high on byte boundaries only and can go high during either
part (instruction or data) of the transfer. During this period, the
serial control port state machine enters a wait state until all data
has been sent. If the system controller decides to abort the
transfer before all of the data is sent, the state machine must be
reset by either completing the remaining transfer or by
returning the CSB low for at least one complete SCLK cycle (but
less than eight SCLK cycles). Raising the CSB on a nonbyte
boundary terminates the serial transfer and flushes the buffer.
In the streaming mode (W1:W0 = 11b), any number of data
bytes can be transferred in a continuous stream. The register
address is automatically incremented or decremented (see the
MSB/LSB First Transfers section). CSB must be raised at the
end of the last byte to be transferred, thereby ending the stream
mode.
Communication Cycle—Instruction Plus Data
There are two parts to a communication cycle with the AD9510.
The first writes a 16-bit instruction word into the AD9510,
coincident with the first 16 SCLK rising edges. The instruction
word provides the AD9510 serial control port with information
regarding the data transfer, which is the second part of the
communication cycle. The instruction word defines whether
the upcoming data transfer is a read or a write, the number of
bytes in the data transfer, and the starting register address for
the first byte of the data transfer.
Write
If the instruction word is for a write operation (I15 = 0b), the
second part is the transfer of data into the serial control port
buffer of the AD9510. The length of the transfer (1, 2, 3 bytes,
or streaming mode) is indicated by 2 bits (W1:W0) in the
instruction byte. CSB can be raised after each sequence of 8 bits
to stall the bus (except after the last byte, where it ends the
cycle). When the bus is stalled, the serial transfer resumes when
CSB is lowered. Stalling on nonbyte boundaries resets the serial
control port.
Since data is written into a serial control port buffer area, not
directly into the AD9510’s actual control registers, an additional
operation is needed to transfer the serial control port buffer
contents to the actual control registers of the AD9510, thereby
causing them to take effect. This update command consists of
writing to Register 5Ah<0> = 1b. This update bit is self-clearing
(it is not required to write 0 to it in order to clear it). Since any
number of bytes of data can be changed before issuing an