AD9510-VCO/PCB Analog Devices Inc, AD9510-VCO/PCB Datasheet - Page 38

• Manufacturer Part Number: AD9510-VCO/PCB
• Description: BOARD EVAL CLOCK DISTR 64LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD9510-VCO/PCB

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

AD9510
Divider Phase Offset
The phase of each output may be selected, depending
on the divide ratio chosen. This is selected by writing the
appropriate values to the registers which set the phase and
start high/low bit for each output. These are the odd numbered
registers from 49h to 57h. Each divider has a 4-bit phase offset
<3:0> and a start high or low bit <4>.
Following a sync pulse, the phase offset word determines how
many fast clock (CLK1 or CLK2) cycles to wait before initiating
a clock output edge. The Start H/L bit determines if the divider
output starts low or high. By giving each divider a different
phase offset, output-to-output delays can be set in increments of
the fast clock period, t
Figure 39 shows four dividers, each set for DIV = 4, 50% duty
cycle. By incrementing the phase offset from 0 to 3, each output
is offset from the initial edge by a multiple of t
For example:
The four outputs may also be described as:
Figure 39. Phase Offset—All Dividers Set for DIV = 4, Phase Set from 0 to 3
CLK1 = 491.52 MHz
t
For DIV = 4
Phase Offset 0 = 0 ns
Phase Offset 1 = 2.0345 ns
Phase Offset 2 = 4.069 ns
Phase Offset 3 = 6.104 ns
OUT1 = 0°
OUT2 = 90°
OUT3 = 180°
OUT4 = 270°
CLK1
CLOCK INPUT
= 1/491.52 = 2.0345 ns
CLK
0
3
× t
1
CLK
CLK
t
2
CLK
.
3
t
2
4
CLK
× t
CLK
5
6
7
8
9 10 11 12 13 14 15
CLK
.
Rev. A | Page 38 of 60
Setting the phase offset to Phase = 4 results in the same relative
phase as the first channel, Phase = 0° or 360°.
In general, by combining the 4-bit phase offset and the Start
H/L bit, there are 32 possible phase offset states (see Table 18).
Table 18. Phase Offset—Start H/L Bit
Phase Offset
(Fast Clock
Rising Edges)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
The resolution of the phase offset is set by the fast clock period
(t
have 32 unique phase offsets available. For any divide ratio, the
number of unique phase offsets is numerically equal to the
divide ratio (see Table 18):
CLK
DIV = 4
Unique Phase Offsets Are Phase = 0, 1, 2, 3
DIV= 7
) at CLK1 or CLK2. As a result, every divide ratio does not
Phase Offset <3:0>
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
49h to 57h
Start H/L <4>
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1