HW-XGI-VIDEO-US Xilinx Inc, HW-XGI-VIDEO-US Datasheet - Page 24

• Manufacturer Part Number: HW-XGI-VIDEO-US
• Description: DAUGHTER CARD VIDEO I/O VIODC
• Manufacturer: Xilinx Inc

Specifications of HW-XGI-VIDEO-US

• Lead Free Status / RoHS Status: Lead free by exemption / RoHS compliant by exemption
• Other names: 122-1506; HW-XGI-VIDEO-US

Chapter 3: Component and S-Video Interfaces
Composite Video Input and Output
24
S-Video Output
ADV7403 S-Video Input
ADV7321 S-Video Output
S-Video Output Signal Conditioning
The Y (intensity) and C (color) conditioned signals are input into the A12 and A10 of the
ADV7403 twelve input analog multiplexer, which routes each of the selected input signals
to one of the ADCs for conversion. Fully automatic detection and selection of all
worldwide standards, (PAL, NTSC and SECAM) is provided as well as vertical blanking
processing for Teletext, Closed Caption and wide screen signaling. For full details
regarding the ADV7403 device refer to the Analog Devices datasheet.
The digital data stream generated from the conversion of the S-Video signals is available to
the FPGA through a 41-bit data bus and 5-bit control. An I2C bus available on the
ADV7403 provides control, status and ancillary data and is directly connected to the
FPGA. For S-Video configuration there are 6 different interface configurations that use
some of the lower 30 pins. The default configuration is to output YCrCb data on the 8-bit
portion of the data bus from P19 to P12.
Generation of S-Video output video from a digital video data stream is accomplished by
the ADV7321 device. Video data is written from the XC2VP4 FPGA into the ADV7321
device, which converts from digital-to-analog values using DAC D and E. The analog
output signals are conditioned to meet specification with the conditioned output going
through connector J20.
Data, video timing control and operations control bus connections between the FPGA and
ADV7321 video encoder provide the digital video data stream and information needed to
convert to generate analog S-Video Y/C signals. The FPGA writes the digital video data
stream and control into the ADV7321, which then produces the appropriate analog output
with complete video timing. The format of the data written is selectable the analog output
is first conditioned and then placed on the output S-Video connector J20.
Figure 3-2
the ADV7321 Y/C analog signal generation. This conditioning circuit is composed of both
active and passive components, with the ADA4410 device providing active circuits and is
designed to meet the specification IEC 60933-5 requirements for S-Video.
Composite video is the format of an analog television (picture only) signal before it is
combined with a sound signal and modulated onto an RF carrier. It is usually in a standard
format such as NTSC, PAL, or SECAM. It is a composite of three source signals called Y, U
and V with sync pulses. Y represents the brightness or luminance of the picture and
includes synchronizing pulses, so that by itself it could be displayed as a monochrome
picture. U and V between them carry the color information.
Composite video input and output is supported on the VIODC card through RCA type
jack J18, this dual RCA jack has the composite video input on X1 and output on X2 and are
color coded yellow. Input signals are conditioned and then presented to the ADV7403 for
conversion to digital video data stream. The ADV7403 device automatically detects the
video standard (PAL, NTSC, SECAM) and converts to the appropriate data stream with
control information. The resulting data stream and control information is transferred to the
details the implementation of the S-Video output conditioning circuit following
www.xilinx.com
Video Input/Output Daughter Card
UG235 (v1.2.1) October 31, 2007
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