HW-XGI-VIDEO-US Xilinx Inc, HW-XGI-VIDEO-US Datasheet - Page 44

• Manufacturer Part Number: HW-XGI-VIDEO-US
• Description: DAUGHTER CARD VIDEO I/O VIODC
• Manufacturer: Xilinx Inc

Specifications of HW-XGI-VIDEO-US

• Lead Free Status / RoHS Status: Lead free by exemption / RoHS compliant by exemption
• Other names: 122-1506; HW-XGI-VIDEO-US

Chapter 6: SDI Interface
SDI Receiver
44
SDI In
ICS664-02
freq control
Equalizer
DCM
Cable
74.25 MHz or
74.1758 MHz
108 MHz
hd_sd
Table 6-1
configured for the three different SDI bit rates. In SD-SDI mode, the 54 MHz clock out of
the ICS664-02 is multiplied by two by a Digital Clock Manager (DCM) to produce the
108 MHz reference clock needed by the RocketIO transceiver in the SDI receiver.
Table 6-1: RocketIO Reference Clock Generation
Figure 6-1
the FPGA.
The serial bitstream enters the RocketIO receiver after passing through an SDI cable
equalizer. The RocketIO receiver must be give a reference clock of the appropriate
frequency depending on the bit rate being received. If the reference clock frequency
doesn’t match the bit rate of the input bitstream the receiver will not lock to the bitstream.
If the demo is in Auto Rx mode, the automatic rate detection logic will sequence the
RocketIO receiver through the three different bit rates supported by the demo until the
receiver locks.
1. It is possible to use 108 MHz instead of 54 MHz for SD-SDI in the transmitter. However, because the ICS664-
1.4835 Gb/s
1.485 Gb/s
02 cannot directly generate 108 MHz, a DCM would be required to generate the 108 MHz clock resulting in
more jitter on the output of the SDI transmitter due to higher jitter on the reference clock. The receiver section
requires 108 MHz and cannot get by with 54 MHz. However, jitter on the RocketIO reference clock is not as
important for the receiver.
270 Mb/s
Bit Rate
RXP
RXN
REFCLKSEL
REFCLK
RXUSRCLK
RXUSRCLK2
REFCLK2
RocketIO
shows the various frequencies produced by the PLL502 and ICS664-02 when
is a block diagram of the SDI receiver. Shaded blocks in the figure are external to
Figure 6-1: SDI Receiver Block Diagram
DIP switches
From ML402
RXRECCLK
RXDATA
Frequency
13.5 MHz
13.5 MHz
Recovery
20
BUFG
54 MHz
SD-SDI
VCXO
Data
www.xilinx.com
Demo Mode
Control
10
Descrambler
27 MHz Clock Enable
HD-SDI
Descrambler
SD-SDI
ICS664-02 Frequency
AutoRate
Detection
74.1758 MHz
74.25 MHz
20
54 MHz
hd_sd
freq control
10
HD-SDI
Framer
SD-SDI
Framer
C
Y
10
10
Video Input/Output Daughter Card
10
UG235 (v1.2.1) October 31, 2007
74.1758 MHz 74.1758 MHz
Rx REFCLK
74.25 MHz
CRC Check
Checker
108 MHz
EDH
hd_sd
10
clk
S
Y
C
Tx REFCLK
ug235_ch5_01_111405
74.25 MHz
54 MHz
HD
Analog
Video
SD
Analog
Video
R