HW-XGI-VIDEO-US Xilinx Inc, HW-XGI-VIDEO-US Datasheet - Page 26

• Manufacturer Part Number: HW-XGI-VIDEO-US
• Description: DAUGHTER CARD VIDEO I/O VIODC
• Manufacturer: Xilinx Inc

Specifications of HW-XGI-VIDEO-US

• Lead Free Status / RoHS Status: Lead free by exemption / RoHS compliant by exemption
• Other names: 122-1506; HW-XGI-VIDEO-US

Chapter 3: Component and S-Video Interfaces
Component Video Input and Output
26
Component Video Input
Input Signal Conditioning
ADV7403 Connection to FPGA
RCA style connector J19 (X1, X3 and X5) enable input of analog component video signals,
which are then converted to the digital domain by the Analog Devices ADV7403 device.
Either YPrPb or RGB analog input signals are accepted. The ADV7403 devices integrated
110 MHz ADCs, with 12-bit resolution, supporting HDTV for 525p, 625p, 720p and 1080i as
well as RGB graphics support from VGA to SXGA at 60 frames per second. The digitized
video output is connected directly to the Xilinx FPGA through a digital data, video timing
control and I
configuration, through ADV7403 video decoder to Xilinx XC2VP4 FPGA.
The three RCA jacks X1, X3 and X5 are color coded Red, Green and Blue respectively and
form the physical connectors for the component video inputs. Conditioning of the analog
input signal is done using circuit detailed in
Digital connections from the ADV7403 to the Xilinx XC2VP4 FPGA consist of 42 data and
5 control signals. The data signals include three 12-bit data busses for, one for each of red,
green and blue pixel values. Control signals include: horizontal and vertical frame
2
GRN
RED
BLU
C control busses.
RCA
RCA
RCA
Figure 3-3: Component Video Input
www.xilinx.com
Conditioning
Conditioning
Conditioning
Figure 3-3
illustrates the VIODC composite video input
Figure
SD/HD Video
ADV7403
Decoder
3-2.
Video Input/Output Daughter Card
UG235 (v1.2.1) October 31, 2007
Clock Generation
Virtex-II Pro
ug235_ch3_05_120805
XC2VP4
R