HW-SPAR3-SK-UNI-G Xilinx Inc, HW-SPAR3-SK-UNI-G Datasheet - Page 24

• Manufacturer Part Number: HW-SPAR3-SK-UNI-G
• Description: KIT STARTER SPARTAN-3
• Manufacturer: Xilinx Inc
• Series: Spartan-3r
• Type: FPGA Configurationr

Specifications of HW-SPAR3-SK-UNI-G

• Contents: Board, Cable, Software, Datasheets and User Manual
• For Use With/related Products: Spartan-3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1521

VGA Signal Timing
24
R
Modern VGA displays support multiple display resolutions, and the VGA controller
dictates the resolution by producing timing signals to control the raster patterns. The
controller produces TTL-level synchronizing pulses that set the frequency at which current
flows through the deflection coils, and it ensures that pixel or video data is applied to the
electron guns at the correct time.
Video data typically comes from a video refresh memory with one or more bytes assigned
to each pixel location. The Spartan-3 Starter Kit board uses three bits per pixel, producing
one of the eight possible colors shown in
data buffer as the beams move across the display. The controller then retrieves and applies
video data to the display at precisely the time the electron beam is moving across a given
pixel.
As shown in
(vertical sync) timings signals and coordinates the delivery of video data on each pixel
clock. The pixel clock defines the time available to display one pixel of information. The VS
signal defines the “refresh” frequency of the display, or the frequency at which all
information on the display is redrawn. The minimum refresh frequency is a function of the
display’s phosphor and electron beam intensity, with practical refresh frequencies in the
60 Hz to 120 Hz range. The number of horizontal lines displayed at a given refresh
frequency defines the horizontal “retrace” frequency.
The signal timings in
25 MHz pixel clock and 60 Hz ±1 refresh.
timing symbols. The timing for the sync pulse width (T
intervals (T
and back porch intervals are the pre- and post-sync pulse times. Information cannot be
displayed during these times.
Table 5-3: 640x480 Mode VGA Timing
Symbol
T
T
T
T
DISP
T
PW
BP
FP
S
FP
Sync pulse time
Display time
Pulse width
Front porch
Back porch
Figure
and T
Parameter
T
BP
5-2, the VGA controller generates the HS (horizontal sync) and VS
PW
Table 5-3
) are based on observations from various VGA displays. The front
www.xilinx.com
Figure 5-3: VGA Control Timing
are derived for a 640-pixel by 480-row display using a
15.36 ms
16.7 ms
320 μs
928 μs
Time
64 μs
T
S
T
Figure 5-3
DISP
Table
Vertical Sync
Spartan-3 FPGA Starter Kit Board User Guide
5-2. The controller indexes into the video
Clocks
416,800
384,000
23,200
1,600
8,000
shows the relation between each of the
PW
) and front and back porch
Lines
521
480
10
29
2
UG130 (v1.2) June 20, 2008
Chapter 5: VGA Port
25.6 μs
3.84 μs
1.92 μs
Horizontal Sync
640 ns
Time
32 μs
UG130_c5_03_051305
T
FP
Clocks
T
800
640
96
16
48
BP