SW006015 Microchip Technology, SW006015 Datasheet - Page 33

• Manufacturer Part Number: SW006015
• Description: C COMPILER MPLAB C32
• Manufacturer: Microchip Technology
• Type: Compilerr
• Series: PIC32r

Specifications of SW006015

• Supported Families: PIC32MX5, MX6, And MX7
• Core Architecture: PIC
• Kit Contents: Software And Docs
• Mcu Supported Families: PIC32 MCUs
• Tool Function: Compiler
• Supported Devices: PIC32 MCUs
• Tool Type: Compiler
• Processor Series: PIC32
• Lead Free Status / RoHS Status: Not applicable / Not applicable
• For Use With/related Products: PIC32
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

© 2007 Microchip Technology Inc.
TABLE 1-9:
-fgcse-lm
-fgcse-sm
-fmove-all-movables
-fno-defer-pop
-fno-peephole
-fno-peephole2
-foptimize-
-fregmove
-freduce-all-givs
-frename-registers
-frerun-cse-after-
-frerun-loop-opt
-fschedule-insns
-fschedule-insns2
-fstrength-reduce
register-move
loop
Option
SPECIFIC OPTIMIZATION OPTIONS (CONTINUED)
When -fgcse-lm is enabled, global common subexpression
elimination attempts to move loads which are only killed by
stores into themselves. This allows a loop containing a
load/store sequence to change to a load outside the loop, and
a copy/store within the loop.
When -fgcse-sm is enabled, a store motion pass is run after
global common subexpression elimination. This pass attempts
to move stores out of loops. When used in conjunction with
-fgcse-lm, loops containing a load/store sequence can
change to a load before the loop and a store after the loop.
Forces all invariant computations in loops to be moved outside
the loop.
Always pop the arguments to each function call as soon as
that function returns. The compiler normally lets arguments
accumulate on the stack for several function calls and pops
them all at once.
Disable machine specific peephole optimizations. Peephole
optimizations occur at various points during the compilation.
-fno-peephole disables peephole optimization on machine
instructions, while -fno-peephole2 disables high level
peephole optimizations. To disable peephole entirely, use both
options.
Attempt to reassign register numbers in move instructions and
as operands of other simple instructions in order to maximize
the amount of register tying.
-fregmove and -foptimize-register-moves are the
same optimization.
Forces all general-induction variables in loops to be
strength-reduced.
These options may generate better or worse code. Results
are highly dependent on the structure of loops within the
source code.
Attempt to avoid false dependencies in scheduled code by
making use of registers left over after register allocation. This
optimization most benefits processors with lots of registers. It
can, however, make debugging impossible, since variables no
longer stay in a “home register”.
Rerun common subexpression elimination after loop
optimizations has been performed.
Run the loop optimizer twice.
Attempt to reorder instructions to eliminate instruction stalls
due to required data being unavailable.
Similar to -fschedule-insns, but requests an additional
pass of instruction scheduling after register allocation has
been done.
Perform the optimizations of loop strength reduction and
elimination of iteration variables.
Definition
DS51686A-page 29