SW006015 Microchip Technology, SW006015 Datasheet - Page 71

• Manufacturer Part Number: SW006015
• Description: C COMPILER MPLAB C32
• Manufacturer: Microchip Technology
• Type: Compilerr
• Series: PIC32r

Specifications of SW006015

• Supported Families: PIC32MX5, MX6, And MX7
• Core Architecture: PIC
• Kit Contents: Software And Docs
• Mcu Supported Families: PIC32 MCUs
• Tool Function: Compiler
• Supported Devices: PIC32 MCUs
• Tool Type: Compiler
• Processor Series: PIC32
• Lead Free Status / RoHS Status: Not applicable / Not applicable
• For Use With/related Products: PIC32
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

© 2007 Microchip Technology Inc.
5.7.2.9.2
This register is a read-only register that captures the most recent virtual address that
caused an Address Error exception (AdEL or AdES).
No initialization is performed on this register in the PIC32MX startup code.
5.7.2.9.3
This register acts as a timer, incrementing at a constant rate, whether or not an
instruction is executed, retired, or any forward progress is made through the pipeline.
The counter increments every other clock, if the DC bit in the Cause register is 0. The
Count register can be written for functional or diagnostic purposes, including at reset
or to synchronize processors. By writing the Count
possible to control whether the Count register continues incrementing while the
processor is in debug mode.
This register is cleared in the PIC32MX startup code.
5.7.2.9.4
This register acts in conjunction with the Count register to implement a timer and timer
interrupt function. The timer interrupt is an output of the core. The Compare register
maintains a stable value and does not change on its own. When the value of the Count
register equals the value of the Compare register, the SI_TimerInt pin is asserted.
This pin remains asserted until the Compare register is written. The SI_TimerInt pin
can be fed back into the core on one of the interrupt pins to generate an interrupt. For
diagnostic purposes, the Compare register is a read/write register. In normal use,
however, the Compare register is write-only. Writing a value to the Compare register,
as a side effect, clears the timer interrupt.
This register is set to 0xFFFFFFFF in the PIC32MX startup code.
5.7.2.9.5
This register is a read/write register that contains the operating mode, interrupt
enabling, and the diagnostic states of the processor. Fields of this register combine to
create operating modes for the processor.
The following settings are initialized by the PIC32MX startup code
(0b000000000x0xx0?00000000000000000):
• Access to Coprocessor 0 not allowed in user mode (CU0 = 0)
• User mode uses configured endianess (RE = 0)
• No change to exception vectors location (BEV = no change)
• No change to flag bits that indicate reason for entry to the reset exception vector
• If CorExtend User Defined Instructions have been implemented
• Interrupt masks are cleared to disable any pending interrupt requests (IM7..IM2
• Interrupt priority level is 0 (IPL = 0)
• Base mode is Kernel mode (UM = 0)
• Error level is normal (ERL = 0)
• Exception level is normal (EXL = 0)
• Interrupts are disabled (IE = 0)
(SR, NMI = no change)
(Config
disabled (CEE = 0).
= 0, IM1..IM0 = 0)
UDI
Bad Virtual Address Register (BadVAddr – CP0 Register 8, Select 0)
Count Register (Count – CP0 Register 9, Select 0)
Compare Register (Compare – CP0 Register 11, Select 0)
Status Register (Status – CP0 Register 12, Select 0)
== 1), CorExtend is enabled (CEE = 1), otherwise, CorExtend is
DM
bit in the Debug register, it is
DS51686A-page 67