SW006015 Microchip Technology, SW006015 Datasheet - Page 74

• Manufacturer Part Number: SW006015
• Description: C COMPILER MPLAB C32
• Manufacturer: Microchip Technology
• Type: Compilerr
• Series: PIC32r

Specifications of SW006015

• Supported Families: PIC32MX5, MX6, And MX7
• Core Architecture: PIC
• Kit Contents: Software And Docs
• Mcu Supported Families: PIC32 MCUs
• Tool Function: Compiler
• Supported Devices: PIC32 MCUs
• Tool Type: Compiler
• Processor Series: PIC32
• Lead Free Status / RoHS Status: Not applicable / Not applicable
• For Use With/related Products: PIC32
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

DS51686A-page 70
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5.7.2.9.16 Config3 Register (Config3 – CP0 Register 16, Select 3)
This register encodes additional capabilities. All fields in the Config3 register are
read-only.
No initialization is performed on this register in the PIC32MX startup code.
5.7.2.9.17 Debug Register (Debug – CP0 Register 23, Select 0)
This register is used to control the debug exception and provide information about the
cause of the debug exception and when re-entering at the debug exception vector due
to a normal exception in debug mode. The read-only information bits are updated every
time the debug exception is taken or when a normal exception is taken when already
in debug mode. Only the DM bit and the EJTAG
non-debug mode. The values of all other bits and fields are UNPREDICTABLE.
Operation of the processor is UNDEFINED if the Debug register is written from
non-debug mode.
No initialization is performed on this register in the PIC32MX startup code.
5.7.2.9.18 Trace Control Register (TraceControl – CP0 Register 23, Select 1)
This register provides control and status information. The TraceControl register is
only implemented if the EJTAG Trace capability is present.
No initialization is performed on this register in the PIC32MX startup code.
5.7.2.10
This register provides additional control and status information. The TraceControl2
register is only implemented if the EJTAG Trace capability is present.
No initialization is performed on this register in the PIC32MX startup code.
5.7.2.10.1 User Trace Data Register (UserTraceData – CP0 Register 23, Select 3)
When this register is written to, a trace record is written indicating a type 1 or type 2
user format. This type is based on the UT bit in the TraceControl register. This
register cannot be written in consecutive cycles. The trace output data is
UNPREDICTABLE if this register is written in consecutive cycles. The
UserTraceData register is only implemented if the EJTAG Trace capability is present.
No initialization is performed on this register in the PIC32MX startup code.
5.7.2.10.2 TraceBPC Register (TraceBPC – CP0 Register 23, Select 4)
This register is used to control start and stop of tracing using an EJTAG hardware
breakpoint. The hardware breakpoint would then be set as a triggered source and
optionally also as a Debug exception breakpoint. The TraceBPC register is only
implemented if both the hardware breakpoints and the EJTAG Trace cap are present.
No initialization is performed on this register in the PIC32MX startup code.
5.7.2.10.3 Debug2 Register (Debug2 – CP0 Register 23, Select 5)
This register holds additional information about Complex Breakpoint exceptions. The
Debug2 register is only implemented if complex hardware breakpoints are present.
No initialization is performed on this register in the PIC32MX startup code.
5.7.2.10.4 Debug Exception Program Counter (DEPC – CP0 Register 24, Select 0)
This register is a read/write register that contains the address at which processing
resumes after a debug exception or debug mode exception has been serviced. For
synchronous (precise) debug and debug mode exceptions, the DEPC contains either:
TRACE CONTROL 2 REGISTER (TraceControl2 – CP0 REGISTER 23,
SELECT 2)
ver
field are valid when read from
© 2007 Microchip Technology Inc.