AD5302 Analog Devices, AD5302 Datasheet
AD5302
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AD5302 Summary of contents
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... V to 5.5 V supply, consuming 230 μ Their on-chip output amplifiers allow the outputs to swing rail- to-rail with a slew rate of 0.7 V/μs. The AD5302/AD5312/AD5322 utilize a versatile 3-wire serial interface that operates at clock rates MHz and is compatible with standard SPI®, QSPI™ ...
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... AD5302/AD5312/AD5322 to 80C51/80L51 Interface.......... 17 AD5302/AD5312/AD5322 to MICROWIRE Interface ........ 17 Applications Information .............................................................. 18 Typical Application Circuit....................................................... 18 Bipolar Operation Using the AD5302/AD5312/AD5322..... 18 Opto-Isolated Interface for Process Control Applications ... 19 Decoding Multiple AD5302/AD5312/AD5322s.................... 19 AD5302/AD5312/AD5322 as a Digitally Programmable Window Detector ....................................................................... 19 ...
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... Rev Page AD5302/AD5312/AD5322 unless otherwise noted. MIN MAX Unit Test Conditions/Comments Bits LSB LSB Guaranteed monotonic by design over all codes Bits LSB LSB Guaranteed monotonic by design over all codes Bits LSB LSB Guaranteed monotonic by design over all codes ...
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... See Terminology section specifications tested with the outputs unloaded. 4 Linearity is tested using a reduced code range: AD5302 (Code 8 to 248); AD5312 (Code 28 to 995); AD5322 (Code 115 to 3981). 5 Guaranteed by design and characterization, not production tested order for the amplifier output to reach its minimum voltage, offset error must be negative. In order for the amplifier output to reach its maximum voltage, ...
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... DB0 Figure 2. Serial Interface Timing Diagram Rev Page AD5302/AD5312/AD5322 Conditions/Comments SCLK Cycle Time SCLK High Time SCLK Low Time SYNC to SCLK Active Edge Setup Time Data Setup Time Data Hold Time SCLK Falling Edge to SYNC Rising Edge ...
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... AD5302/AD5312/AD5322 OUTPUT IDEAL VOLTAGE ACTUAL POSITIVE OFFSET DAC CODE ERROR DEADBAND AMPLIFIER FOOTROOM (1mV) NEGATIVE OFFSET ERROR Figure 3. Transfer Function with Negative Offset GAIN ERROR OFFSET ERROR ACTUAL OUTPUT VOLTAGE IDEAL POSITIVE OFFSET ERROR DAC CODE Figure 4. Transfer Function with Positive Offset Rev ...
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... This is a stress rating only; functional operation of the device at these or any + 0.3 V other conditions above those indicated in the operational DD + 0.3 V section of this specification is not implied. Exposure to absolute DD maximum rating conditions for extended periods may affect + 0 device reliability. )/θ Rev Page AD5302/AD5312/AD5322 ...
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... Serial Data Input. This device has a 16-bit input shift register. Data is clocked into the register on the falling edge of the serial clock input. The DIN input buffer is powered down after each write cycle. 10 GND Ground Reference Point for All Circuitry on the Part. LDAC GND 1 10 AD5302/ V DIN AD5312 ...
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... This is the glitch impulse transferred to the output of one DAC due to a change in the output of the other DAC measured by loading one of the input registers with a full-scale code AD5302/AD5312/AD5322 change (all 0s to all 1s and vice versa) while keeping LDAC high, then pulsing LDAC low, and monitoring the output of the DAC whose digital code is not changed ...
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... Rev Page 0 25° 0.2 0.1 0 –0.1 –0.2 –0 100 150 CODE Figure 9. AD5302 Typical DNL Plot 0 25° 0.4 0.2 0 –0.2 –0.4 –0.6 0 200 400 600 CODE Figure 10. AD5312 Typical DNL Plot 1 25°C ...
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... REF 0.75 0.50 MAX DNL MAX INL 0.25 0 –0.25 MIN INL MIN DNL –0.50 –0.75 –1.00 – TEMPERATURE(°C) Figure 13. AD5302 INL Error and DNL Error vs. Temperature 1 =2V REF 0.5 GAIN ERROR 0 –0.5 OFFSET ERROR –1.0 – TEMPERATURE(°C) Figure 14. Offset Error and Gain Error vs. Temperature ...
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... AD5302/AD5312/AD5322 600 BOTH DACS IN GAIN-OF-TWO MODE REFERENCE INPUTS BUFFERED 500 400 –40°C 300 +105°C 200 100 0 2.5 3.0 3.5 4.0 V (V) DD Figure 18. Supply Current vs. Supply Voltage 1.0 BOTH DACS IN THREE-STATE CONDITION 0.8 0.6 0.4 +25°C 0.2 0 2.7 3.2 3.7 4.2 V (V) DD Figure 19. Power-Down Current vs. Supply Voltage 700 T = 25°C ...
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... FREQUENCY(Hz) Figure 25. Multiplying Bandwidth (Small-Signal Frequency Response) 1 0.5 0 –0.5 –1 10M Rev Page AD5302/AD5312/AD5322 500ns/DIV Figure 26. DAC-to-DAC Crosstalk 25° (V) REF Figure 27. Full-Scale Error vs. V (Buffered) REF 5 ...
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... The slew rate is 0.7 V/μs with a half-scale settling time OUT ±0.5 LSB (at eight bits μs. See Figure 21. OUTPUT BUFFER AMPLIFIER POWER-ON RESET The AD5302/AD5312/AD5322 are provided with a power-on reset function to power them defined state. The power- on state is • Normal operation • Reference inputs unbuffered • ...
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... The remaining bits are DAC data bits, starting with the MSB and ending with the LSB. The AD5322 uses all 12 bits of DAC data, the AD5312 uses 10 bits and ignores the 2 LSB. The AD5302 uses eight bits and ignores the last four bits. The data format is straight binary, with all 0s corresponding output, and all 1s corresponding to full-scale output (VREF – ...
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... AD5302/AD5312/AD5322 POWER-DOWN MODES The AD5302/AD5312/AD5322 have very low power consump- tion, dissipating only 0.7 mW with supply and 1.5 mW with supply. Power consumption can be further reduced when the DACs are not in use by putting them into one of three power-down modes, which are selected by Bit 13 and Bit 12 (PD1 and PD0) of the control word ...
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... The SYNC signal is again derived from a bit programmable pin on the port. In this case, port line P3.3 is used. When data transmitted to the AD5302/ AD5312/AD5322, P3.3 is taken low. The 80C51/80L51 transmit data in 8-bit bytes only; thus only eight falling clock edges occur in the transmit cycle ...
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... AD5302/AD5312/AD5322 APPLICATIONS INFORMATION TYPICAL APPLICATION CIRCUIT The AD5302/AD5312/AD5322 can be used with a wide range of reference voltages, especially if the reference inputs are configured to be unbuffered, in which case the devices offer full, one-quadrant multiplying capability over a reference range More typically, the AD5302/AD5312/AD5322 can DD be used with a fixed, precision reference voltage ...
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... AD5302/AD5312/AD5322 from the controller. This can easily be achieved by using opto-isolators, which provide isolation in excess of 3 kV. The serial loading structure of the AD5302/ AD5312/AD5322 makes them ideally suited for use in opto- isolated applications. Figure 41 shows an opto-isolated interface to the AD5302/AD5312/AD5322 where DIN, SCLK, and SYNC are driven from opto-couplers ...
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... The printed circuit board on which the AD5302/AD5312/AD5322 is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. If the AD5302/ AD5312/AD5322 are in a system where multiple devices require an AGND-to-DGND connection, the connection should be made at one point only ...
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... OUTLINE DIMENSIONS IDENTIFIER 3.10 3.00 2.90 5. 3.10 4.90 3.00 4.65 1 2.90 5 PIN 1 0.50 BSC 0.95 15° MAX 0.85 1.10 MAX 0.75 0.15 0.23 6° 0.30 0.05 0.13 0° 0.15 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-BA Figure 45. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters Rev Page AD5302/AD5312/AD5322 0.70 0.55 0.40 ...
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... AD5302ARMZ-REEL −40°C to +105°C AD5302ARMZ-REEL7 −40°C to +105°C AD5302BRM −40°C to +105°C AD5302BRM-REEL −40°C to +105°C AD5302BRM-REEL7 −40°C to +105°C AD5302BRMZ −40°C to +105°C AD5302BRMZ-REEL −40°C to +105°C AD5302BRMZ-REEL7 −40°C to +105°C AD5312ARM − ...
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... NOTES AD5302/AD5312/AD5322 Rev Page ...
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... AD5302/AD5312/AD5322 NOTES ©2006-2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00928-0-5/11(D) Rev Page ...