AD5325 Analog Devices, AD5325 Datasheet

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AD5325

Manufacturer Part Number
AD5325
Description
Manufacturer
Analog Devices
Datasheet

Specifications of AD5325

Resolution (bits)
12bit
Dac Update Rate
125kSPS
Dac Settling Time
8µs
Max Pos Supply (v)
+5.5V
Single-supply
Yes
Dac Type
Voltage Out
Dac Input Format
I2C/Ser 2-wire,Ser

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FEATURES
AD5305: 4 buffered 8-bit DACs in 10-lead MSOP
AD5315: 4 buffered 10-bit DACs in 10-lead MSOP
AD5325: 4 buffered 12-bit DACs in 10-lead MSOP
Low power operation: 500 μA @ 3 V, 600 μA @ 5 V
2-wire (I
2.5 V to 5.5 V power supply
Guaranteed monotonic by design over all codes
Power-down to 80 nA @ 3 V, 200 nA @ 5 V
Three power-down modes
Double-buffered input logic
Output range: 0 V to V
Power-on reset to 0 V
Simultaneous update of outputs (LDAC function)
Software clear facility
Data readback facility
On-chip rail-to-rail output buffer amplifiers
Temperature range: −40°C to +105°C
APPLICATIONS
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
Industrial process control
Rev. G
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
A version: ±1 LSB INL, B version: ±0.625 LSB INL
A version: ±4 LSB INL, B version: ±2.5 LSB INL
A version: ±16 LSB INL, B version: ±10 LSB INL
2
C®-compatible) serial interface
REF
SDA
SCL
A0
INTERFACE
LOGIC
POWER-ON
RESET
LDAC
FUNCTIONAL BLOCK DIAGRAM
Quad Voltage Output, 8-/10-/12-Bit DACs
2.5 V to 5.5 V, 500 μA, 2-Wire Interface
V
REGISTER
REGISTER
REGISTER
REGISTER
DD
INPUT
INPUT
INPUT
INPUT
AD5305/AD5315/AD5325
GND
Figure 1.
REGISTER
REGISTER
REGISTER
REGISTER
DAC
DAC
DAC
DAC
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
GENERAL DESCRIPTION
The AD5305/AD5315/AD5325
buffered voltage output DACs in a 10-lead MSOP that operate
from a single 2.5 V to 5.5 V supply, consuming 500 μA at 3 V.
Their on-chip output amplifiers allow rail-to-rail output swing
with a slew rate of 0.7 V/μs. A 2-wire serial interface that
operates at clock rates up to 400 kHz is used. This interface is
SMBus compatible at V
placed on the same bus.
The references for the four DACs are derived from one
reference pin. The outputs of all DACs can be updated
simultaneously using the software LDAC function.
The parts incorporate a power-on reset circuit, which ensures
that the DAC outputs power up to 0 V and remain there until a
valid write takes place to the device. There is also a software
clear function to reset all input and DAC registers to 0 V. The
parts contain a power-down feature that reduces the current
consumption of the devices to 200 nA @ 5 V (80 nA @ 3 V).
The low power consumption of these parts in normal operation
makes them ideally suited for portable battery-operated equip-
ment. The power consumption is 3 mW at 5 V, 1.5 mW at 3 V,
reducing to 1 μW in power-down mode.
1
Protected by U.S. Patent No. 5,969,657 and 5,684,481.
STRING
STRING
STRING
STRING
REF IN
DAC A
DAC B
DAC C
DAC D
BUFFER
BUFFER
BUFFER
BUFFER
POWER-DOWN
AD5305/AD5315/AD5325
LOGIC
DD
©2006 Analog Devices, Inc. All rights reserved.
V
V
V
V
< 3.6 V. Multiple devices can be
OUT
OUT
OUT
OUT
A
B
C
D
1
are quad 8-, 10-, and 12-bit
www.analog.com

Related parts for AD5325

AD5325 Summary of contents

Page 1

... A version: ±1 LSB INL, B version: ±0.625 LSB INL AD5315: 4 buffered 10-bit DACs in 10-lead MSOP A version: ±4 LSB INL, B version: ±2.5 LSB INL AD5325: 4 buffered 12-bit DACs in 10-lead MSOP A version: ±16 LSB INL, B version: ±10 LSB INL Low power operation: 500 μ 600 μ ...

Page 2

... Read Operation........................................................................... 17 Double-Buffered Interface ........................................................ 18 Power-Down Modes .................................................................. 18 Applications..................................................................................... 20 Typical Application Circuit....................................................... 20 Bipolar Operation....................................................................... 20 Multiple Devices on One Bus ................................................... 20 AD5305/AD5315/AD5325 as a Digitally Programmable Window Detector ....................................................................... 21 Coarse and Fine Adjustment Using the AD5305/AD5315/AD5325 ....................................................... 21 Power Supply Decoupling ......................................................... 21 Outline Dimensions ....................................................................... 23 Ordering Guide .......................................................................... 23 Added Octals Section to Table II.................................................. 18 Updated Outline Dimensions....................................................... 19 4/01— ...

Page 3

... V − V − 0.001 0.001 0.5 0 2.5 2 Rev Page AD5305/AD5315/AD5325 unless otherwise noted. MIN MAX Unit Conditions/Comments Bits LSB LSB Guaranteed monotonic by design over all codes Bits LSB LSB Guaranteed monotonic by design over all codes Bits LSB LSB ...

Page 4

... See the Terminology section specifications tested with the outputs unloaded. 4 Linearity is tested using a reduced code range: AD5305 (Code 8 to 248); AD5315 (Code 28 to 995); AD5325 (Code 115 to 3981). 5 Guaranteed by design and characterization, not production tested. 6 For the amplifier output to reach its minimum voltage, offset error must be negative; to reach its maximum voltage, V positive ...

Page 5

... Capacitive load for each bus line min of the SCL signal) in order to bridge the undefined region of SCL’s IH and t measured between 0.3 V and 0 Rev Page AD5305/AD5315/AD5325 unless otherwise noted. MIN MAX Conditions/Comments REF DD ¼ scale to ¾ scale change (0×40 to 0×C0) ¼ ...

Page 6

... AD5305/AD5315/AD5325 SDA SCL t 4 START CONDITION Figure 2. 2-Wire Serial Interface Timing Diagram Rev Page REPEATED STOP START CONDITION CONDITION t 8 ...

Page 7

... V other conditions above those indicated in the operational DD + 0.3 V section of this specification is not implied. Exposure to absolute DD + 0.3 V maximum rating conditions for extended periods may affect DD + 0.3 V device reliability. DD )/θ Rev Page AD5305/AD5315/AD5325 ...

Page 8

... Clock rates 400 kb/s can be accommodated in the 2-wire interface Address Input. Sets the least significant bit of the 7-bit slave address AD5305 SCL 2 9 OUT AD5315/ AD5325 V B SDA 8 3 OUT TOP VIEW V C GND 7 4 OUT (Not to Scale ...

Page 9

... CODE Figure 5. AD5315 Typical INL Plot 25° –4 –8 –12 0 1000 2000 CODE Figure 6. AD5325 Typical INL Plot 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 200 250 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 800 1000 1.0 0.5 0 –0.5 –1.0 3000 4000 Rev ...

Page 10

... AD5305/AD5315/AD5325 0. 25°C A 0.25 MAXINL 0 MIN DNL –0.25 MIN INL –0. (V) REF Figure 10. AD5305 INL and DNL Error vs REF 0.3 MAX INL 0.2 MAX DNL 0.1 0 –0.1 MIN DNL –0.2 –0.3 MIN INL –0.4 –0.5 – TEMPERATURE (°C) Figure 11 ...

Page 11

... Figure 19. Half-Scale Settling (1/4 to 3/4 Scale Code Change) CH1 CH2 CH1 2V, CH2 200mV, TIME BASE = 200µs/DIV 5.0 5.5 DECREASING INCREASING CH1 CH2 CH1 500mV, CH2 5V, TIME BASE = 1µs/DIV 4 5 Rev Page AD5305/AD5315/AD5325 T = 25° REF V A OUT SCL T = 25° ...

Page 12

... DD 300 350 400 450 500 I (µA) DD Figure 22. I Histogram with and 2.50 2.49 2.48 2.47 1µs/DIV Figure 23. AD5325 Major-Code Transition Glitch Energy 10 0 –10 –20 –30 –40 –50 –60 10 100 1k 10k FREQUENCY (Hz) Figure 24. Multiplying Bandwidth (Small-Signal Frequency Response 550 600 ...

Page 13

... This is the difference between an ideal sine wave and its attenuated version using the DAC. The sine wave is used as the reference for the DAC and the THD is a measure of the harmonics present on the DAC output measured in dB. Rev Page AD5305/AD5315/AD5325 ...

Page 14

... AD5305/AD5315/AD5325 OUTPUT IDEAL VOLTAGE ACTUAL NEGATIVE OFFSET DAC CODE ERROR DEAD BAND CODES AMPLIFIER FOOTROOM (1mV) NEGATIVE OFFSET ERROR Figure 27. Transfer Function with Negative Offset GAIN ERROR PLUS OFFSET ERROR OUTPUT VOLTAGE POSITIVE OFFSET Rev Page GAIN ERROR PLUS OFFSET ERROR ...

Page 15

... The slew rate is 0.7 V/μs with a half-scale settling time to ±0.5 LSB (at eight bits μs. POWER-ON RESET V A OUT The AD5305/AD5315/AD5325 are provided with a power-on reset function, so that they power defined state. The OUTPUT BUFFER AMPLIFIER power-on state is • Normal operation • ...

Page 16

... LDAC READ/WRITE SEQUENCE the case of the AD5305/AD5315/AD5325, all write access sequences and most read sequences begin with the device address (with followed by the pointer byte. This pointer byte specifies the data format and determines which DAC is being accessed in the subsequent read/write operation (see Figure 31) ...

Page 17

... MSB MOST SIGNIFICANT DATA BYTE WRITE OPERATION When writing to the AD5305/AD5315/AD5325 DACs, the user must begin with an address byte ( 0), after which the DAC acknowledges that it is prepared to receive data by pulling SDA low. This address byte is followed by the pointer byte, which is also acknowledged by the DAC ...

Page 18

... LDAC is brought low, the DAC registers are filled with the contents of the input registers. In the case of the AD5305/AD5315/ AD5325, the part updates the DAC register only if the input register has been changed since the last time the DAC register was updated, thereby removing unnecessary digital crosstalk. ...

Page 19

... DAC amplifier. There are three different options. The output is connected internally to GND through a 1 kΩ resistor, a 100 kΩ resistor left open-circuited (three-state). Resistor tolerance = ±20%. The output stage is illustrated in Figure 35. AD5305/AD5315/AD5325 RESISTOR AMPLIFIER STRING DAC POWER-DOWN CIRCUITRY Figure 35 ...

Page 20

... AD5305/AD5315/AD5325 APPLICATIONS TYPICAL APPLICATION CIRCUIT The AD5305/AD5315/AD5325 can be used with a wide range of reference voltages where the devices offer full, one-quadrant multiplying capability over a reference range More typically, these devices are used with a fixed, precision reference voltage. Suitable references for 5 V operation are the AD780 and REF192 (2 ...

Page 21

... Figure 39. Window Detection COARSE AND FINE ADJUSTMENT USING THE AD5305/AD5315/AD5325 Two of the DACs in the AD5305/AD5315/AD5325 can be paired together to form a coarse and fine adjustment function, as shown in Figure 40. DAC A is used to provide the coarse adjustment while DAC B provides the fine adjustment. Varying the ratio of R1 and R2 changes the relative effect of the coarse and fine adjustments ...

Page 22

... AD5312 10 2 AD5322 12 2 AD5303 8 2 AD5313 10 2 AD5323 12 2 QUADS AD5304 8 4 AD5314 10 4 AD5324 12 4 AD5305 8 4 AD5315 10 4 AD5325 12 4 AD5306 8 4 AD5316 10 4 AD5326 12 4 AD5307 8 4 AD5317 10 4 AD5327 12 4 OCTALS AD5308 8 8 AD5318 10 8 AD5328 12 8 Table 10 ...

Page 23

... AD5325ARMZ −40°C to +105°C AD5325BRM −40°C to +105°C AD5325BRM-REEL −40°C to +105°C AD5325BRM-REEL7 −40°C to +105°C 1 AD5325BRMZ −40°C to +105°C 1 AD5325BRMZ-REEL −40°C to +105°C 1 AD5325BRMZ-REEL7 −40°C to +105° Pb-free part; # denotes lead-free product may be top or bottom marked. ...

Page 24

... AD5305/AD5315/AD5325 NOTES Purchase of licensed components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I 2 Rights to use these components system, provided that the system conforms to the I ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners ...

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