MPC8360VVALFH Freescale Semiconductor, MPC8360VVALFH Datasheet
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MPC8360VVALFH
Specifications of MPC8360VVALFH
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MPC8360VVALFH Summary of contents
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... Rev locate any updates for this document, refer to the MPC8360E product summary page on our website listed on the back cover of this document or contact your Freescale sales office. © 2011 Freescale Semiconductor, Inc. All rights reserved. Document Number: MPC8360EEC Rev. 4, 01/2011 Contents 1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 ...
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... Figure 1. MPC8360E Block Diagram System Interface Unit (SIU) Memory Controllers GPCM/UPM/SDRAM DDRC1 32/64 DDR Interface Unit DDRC2 PCI PCI Bridge Local Local Bus Bus Arbitration DUART Dual I2C 4 Channel DMA Interrupt Controller Protection & Configuration System Reset Clock Synthesizer Freescale Semiconductor ...
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... MHz (for the MPC8360E) and 400 MHz (for the MPC8358E) — Serial DMA channel for receive and transmit on all serial channels MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor Security Engine Multi-User RAM Serial DMA & ...
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... POS hardware; microcode must be loaded as an IRAM package – Transparent up to 70-Mbps full-duplex – HDLC up to 70-Mbps full-duplex – HDLC BUS Mbps 1.SMII or SGMII media-independent interface is not currently supported. MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev Freescale Semiconductor ...
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... Data encryption standard execution unit (DEU) – DES, 3DES – Two key (K1, K2) or three key (K1, K2, K3) – ECB and CBC modes for both DES and 3DES — Advanced encryption standard unit (AESU) MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor Overview 5 ...
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... On-the-fly power management using CKE — Registered DIMM support — 2.5-V SSTL2 compatible I/O for DDR1, 1.8-V SSTL2 compatible I/O for DDR2 — External driver impedance calibration — On-die termination (ODT) MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev Freescale Semiconductor ...
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... Four groups of interrupts with programmable priority — External and internal interrupts directed to communication processor — Redirects interrupts to external INTA pin when in core disable mode — Unique vector number for each interrupt source MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor Overview 7 ...
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... MPC8360E/58E. The device is currently targeted to these specifications. Some of these specifications are independent of the I/O cell, but are included for a more complete reference. These are not purely I/O buffer design specifications. MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev interfaces 2 C-1 EPROM by boot sequencer Freescale Semiconductor ...
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... IN REF the PCI interface may overshoot/undershoot according to the PCI Electrical Specification for 3.3-V operation shown in Figure 4. MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor Table 1. Absolute Maximum Ratings Symbol DDR DDR2 LV ...
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... V ± 125 mV 1.8 V ± 3.3 V ± 330 2.5 V ± 125 3.3 V ± 330 2.5 V ± 125 3.3 V ± 330 2.5 V ± 125 mV OV 3.3 V ± 330 ° 105 J –40 to 105 Freescale Semiconductor are Notes 1 1 — — — — — 2 ...
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... Overvoltage Waveform Undervoltage Waveform Figure 4. Maximum AC Waveforms on PCI interface for 3.3-V Signaling MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor + 5% DD GND Not to Exceed 10 interface refers to the clock period associated with the bus clock interface. ...
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... MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev Table 3. Output Drive Capability Output Impedance (Ω (half-strength mode (half-strength mode and and OV ) and assert PORESET before the power Supply Voltage 2.5 2.5/3 and I/O supply voltages DD Figure 5. Freescale Semiconductor ...
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... MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor I/O Voltage (GV Core Voltage (V Figure 5. Power Sequencing Example , and not have any ordering requirements with respect to one DD DD Table 4 QUICC Engine ...
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... Dhrystone benchmark J target, and I 105°C, and an artificial smoke test 70°C, and a Dhrystone benchmark J 1 Typical Maximum Unit 4.1 4.5 W 4.5 5.0 W Table 6. = 105°C, and a Dhrystone benchmark J target, and I 105°C, and an artificial smoke test. J Freescale Semiconductor Notes Notes ...
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... This section provides the clock input DC and AC electrical characteristics for the MPC8360E/58E. The rise/fall time on QUICC Engine block input pins should not exceed 5 ns. This should be enforced especially on clock signals. Rise time refers to signal transitions from 10 from 90 MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor ...
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... CLKIN — — Min Max 2 0 –0.3 0.4 IL — ±10 IN — ±10 IN — ±100 IN Table 8 provides the clock input Typical Max Unit — 66.67 MHz — — ns 1.0 2.3 ns — — ±150 ps Freescale Semiconductor Unit V V μA μA μA Notes 1 — ...
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... Table 10. RESET Pins DC Electrical Characteristics Characteristic Input high voltage Input low voltage Input current Output high voltage Output low voltage MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor = 2.5 ± 0.125 mV/ 3.3 V ± 165 mV DD Symbol Min t — G125 t — ...
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... MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev Symbol Condition 3 not relevant for those pins. OH Min 512 — 1 Min Max Unit — 0.4 V Max Unit Notes — PCI_SYNC_IN — CLKIN — PCI_SYNC_IN — PCI_SYNC_IN — PCI_SYNC_IN — CLKIN — PCI_SYNC_IN — — PCI_SYNC_IN Freescale Semiconductor ...
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... SPI (master/slave) UCC through TDM MCC UTOPIA L2 POS-PHY L2 HDLC bus HDLC/transparent MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor Table 12. PLL and DLL Lock Times Min — 7680 Section 22, “Clocking,” NOTE Interface Operating Max Interface Bit ...
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... OL I — VREF Min QUICC Engine Operating 1 Frequency (MHz) 115 (Kbps (typ Max Unit 1.89 V 0.51 × 0.04 V REF – 0.125 V REF μA ±10 — mA — mA μA ±10 Freescale Semiconductor Notes — — — Notes — — 4 — — — ...
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... It is the supply to which far end signal termination is made and is expected equal This rail should track variations in the DC level of MV REF 4. Output leakage is measured with all outputs disabled MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor Symbol Min I — all times. ...
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... V ± 5%. DD Symbol Min V — 0.31 IH REF (typ Min Max Unit — 0 /2, V (peak-to-peak) = 0.2 V. OUT DD OUT (typ Max Unit MV – 0.25 V REF — V Max Unit MV – 0.31 V REF — V Freescale Semiconductor Notes 1 1 Notes — — Notes — — ...
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... Table 21. DDR and DDR2 SDRAM Output AC Timing Specifications for Source At recommended operating conditions with GV 8 Parameter MCK[n] cycle time, (MCK[n]/MCK[n] crossing) Skew between any MCK to ADDR/CMD MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor of (1.8 or 2.5 V) ± 5%. DD Symbol Min t DISKEW 333 MHz – ...
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... DDKHMP Min Max Unit — ns 2.1 2.8 3.5 — ns 2.0 2.7 2.8 3.5 — ns 2.1 2.8 3.5 — ns 2.0 2.7 3.5 –0.8 0.7 ns — ns 0.7 1.0 1.2 — ns 0.7 1.0 1.2 –0.5 × t – 0.6 + 0.6 ns MCK MCK Freescale Semiconductor Notes ...
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... In rev. 2.0 silicon, due to errata, t DDKHMH –0.9 ns. Refer to Errata DDR18 in Chip Errata for the MPC8360E, Rev MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor Synchronous Mode (continued 2.5 V) ± 5%. DD ...
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... MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev MCK[n] MCK[n] t MCK t AOSKEW(max) CMD t AOSKEW(min) CMD AOSKEW = 50 Ω Figure 8. DDR AC Test Load DDR DDR2 ± 0. REF REF 0.5 × GV 0.5 × NOOP NOOP Measurement Ω Unit ± 0. Freescale Semiconductor Notes 1 2 ...
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... OH = 100 μA Low-level output voltage Input current (0 V ≤V ≤ Note: 1. Note that the symbol this case, represents the OV IN MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor t MCK DDKHAS DDKHCS DDKHAX DDKHCX NOOP DDKHMP t DDKHMH ...
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... Specification Version 1.3. The RMII interface follows the RMII Consortium RMII Specification Version 1.2. MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev Table 24. DUART AC Timing Specifications Parameter Section 8.3, “Ethernet Management Interface Electrical Value Unit Notes 256 baud — >1,000,000 baud 1 16 — 2 Freescale Semiconductor ...
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... GTX_CLK clock period GTX_CLK duty cycle GTX_CLK to GMII data TXD[7:0], TX_ER, TX_EN delay GTX_CLK clock rise time, (20% to 80%) MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor UCC Ethernet Controller: Three-Speed Ethernet, MII Management Conditions — –4.0 mA ...
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... GMII transmit timing GTKHDV GTX t GTXR Min Typ Max Unit — 8.0 — — 2.0 — — ns 0.2 — — ns — — 1.0 ns Freescale Semiconductor Notes — for inputs clock Notes — — — 2 — ...
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... TX_CLK clock period 10 Mbps TX_CLK clock period 100 Mbps TX_CLK duty cycle TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor UCC Ethernet Controller: Three-Speed Ethernet, MII Management /OV of 3.3 V ± 10%. DD ...
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... MRDVKH t MRDXKH t MRXR 1 Min Typ Max 1.0 — 4.0 1.0 — 4.0 symbolizes MII transmit MTKHDX t MTXR 1 Min Typ Max — 400 — — 40 — 35 — 65 10.0 — — 10.0 — — 1.0 — 4.0 Freescale Semiconductor Unit ns ns for Unit ...
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... AC test load. Output Figure 14 shows the MII receive AC timing diagram. RX_CLK RXD[3:0] RX_DV RX_ER MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor UCC Ethernet Controller: Three-Speed Ethernet, MII Management /OV of 3.3 V ± 10 Symbol t MRXF (first two letters of functional block)(signal)(state)(reference)(state) for outputs ...
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... RMII(RM) reference (X) clock. For rise and fall times, the latter RMX t RMX t t RMXH RMXF t RMTKHDX 1 Min Typ Max — 20 — 35 — — — — 10 1.0 — 4.0 1.0 — 4.0 symbolizes RMII RMTKHDX t RMXR Freescale Semiconductor Unit for ...
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... AC test load. Output Figure 17 shows the RMII receive AC timing diagram. REF_CLK RXD[1:0] CRS_DV RX_ER MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor UCC Ethernet Controller: Three-Speed Ethernet, MII Management /OV of 3.3 V ± 10 Symbol t RMX ...
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... Min Typ Max Unit — 8.0 — — 1.0 — — ns — 5.0 — — 1.0 ns — — 1.0 ns — 8.0 — — symbolizes the TBI TTKHDV (K) going high TTX t TTXR t TTKHDX Freescale Semiconductor Notes — — 3 — — 2 — for ...
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... RCG are measured from riding edge of PMA_RX_CLK0. Figure 19 shows the TBI receive AC timing diagram. PMA_RX_CLK1 RCG[9:0] PMA_RX_CLK0 MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor UCC Ethernet Controller: Three-Speed Ethernet, MII Management /OV of 3.3 V ± 10 ...
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... Notes — — ns 0.5 — — ns 2.6 8.0 8 — 0.75 ns — 0.75 ns 8.0 — ns — the lowest speed transitioned RGT maximum for UCC1, 1.2 ns for UCC2 minimum is –0.65 ns for UCC2 option 1 minimum for rev. 2.1 SKRGTKHDX Freescale Semiconductor — — 6 — ...
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... Table 36. MII Management DC Electrical Characteristics When Powered at 3.3 V Parameter Supply voltage (3.3 V) Output high voltage Output low voltage Input high voltage MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor UCC Ethernet Controller: Three-Speed Ethernet, MII Management t RGTH t SKRGTKHDX TXD[8:5] ...
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... Min Max — 0.80 — ±10 Typ Max Unit Notes 2.5 — MHz 400 — ns — — ns — — ns 110 — — ns — — ns — — symbolizes management MDKHDX Freescale Semiconductor Unit V μA 2 — — 3 — — — — for ...
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... Inputs need to be stable at least one TMR clock. 9 Local Bus This section describes the DC and AC electrical specifications for the local bus interface of the MPC8360E/58E. MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor t MDC t t MDHF MDCH ...
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... LBOTOT1 t 3.0 — LBOTOT2 t 2.5 — LBOTOT3 t — 4.5 LBKHLR t — 4.5 LBKHOV1 t — 4.5 LBKHOV2 t — 4.5 LBKHOV3 t 1.0 — LBKHOX1 t 1.0 — LBKHOX2 Freescale Semiconductor Max Unit + 0.3 V 0.8 V — V 0.2 V μA ±10 Unit Notes — ns — ...
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... LALE output fall to LAD output transition (LATCH hold time) LALE output fall to LAD output transition (LATCH hold time) Local bus clock to output valid MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor Symbol t LBKHOZ (first two letters of functional block)(signal)(state)(reference)(state) for outputs ...
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... LBK /2 of the rising/falling edge of LCLK0 to 0.4 × Ω Figure 22. Local Bus C Test Load 1 Min Max Unit — symbolizes local bus LBIXKH1 clock reference (K) goes high (H), in this case for of the signal in question for 3.3 Ω L Freescale Semiconductor Notes — for ...
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... Input Signal: LGTA Output Signals: LSDA10/LSDWE/LSDRAS/ LSDCAS/LSDDQM[0:3] LA[27:31]/LBCTL/LBCKE/LOE/ Output Signals: LAD[0:31]/LDP[0:3] LALE Figure 24. Local Bus Signals, Nonspecial Signals Only (DLL Bypass Mode) MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor t LBIVKH t t LBKHOX LBKHOV t LBKHOZ t t ...
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... LCS[0:3]/LBS[0:3]/LGPL[0:5] Figure 26. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV (DLL Bypass Mode) MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev LBKHOZ1 t LBKHOV1 t LBIVKH2 t LBIVKH1 t LBKHOZ1 t LBKHOV1 t LBKHOZ t LBKHOV t LBIVKH t LBKHOZ t LBKHOV t LBIXKH2 t LBIXKH1 t LBIXKH t LBIXKH t LBIVKH Freescale Semiconductor ...
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... Input Signals: LAD[0:31]/LDP[0:3] (DLL Bypass Mode) UPM Mode Output Signals: LCS[0:3]/LBS[0:3]/LGPL[0:5] Figure 27. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV (DLL Bypass Mode) MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor t LBKHOZ t LBKHOV t LBIVKH ...
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... MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev LBKHOZ1 t LBKHOV1 t LBIVKH2 t LBIVKH1 t LBKHOZ1 t LBKHOV1 Symbol Condition – — — ≤ V ≤ LBIXKH2 t LBIXKH1 Min Max Unit 2.4 — V — 0.5 V — 0 –0.3 0.8 V μA — ±10 Freescale Semiconductor ...
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... TRST is an asynchronous level sensitive signal. The setup time is for test purposes only. 4. Non-JTAG signal input timing with respect Non-JTAG signal output timing with respect Guaranteed by design and characterization. MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor Table 2). Symbol f ...
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... MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev Ω JTKHKL t JTG VM = Midpoint Voltage ( TRST VM = Midpoint Voltage (OV DD /2) Figure 31. TRST Timing Diagram VM t JTDVKH t JTKLDV t JTKLDZ VM = Midpoint Voltage (OV DD /2) Figure 32. Boundary-Scan Timing Diagram Ω JTGR t JTGF JTDXKH Input Data Valid Output Data Valid Freescale Semiconductor ...
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... JTAG External Clock TDI, TMS t JTKLOX TDO TDO Output Data Valid Figure 33. Test Access Port Timing Diagram MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor JTIVKH Input Data Valid t JTKLOV Output Data Valid t ...
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... Min Max Unit 0.7 × 0 0.3 × OV –0 0 0.1 × C 250 — μA — ±10 1 Min Max 0 400 I2C 1.3 — 0.6 — 0.6 — 0.6 — 100 — Freescale Semiconductor Notes — — — 4 Unit kHz μs μs μs μs ns ...
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... AC test load for the I Output Figure 35 shows the AC timing diagram for the I SDA t I2CF t I2CL SCL t I2SXKL S MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor Electrical Specifications (continued) Table 44). Symbol t I2DXKL CBUS compatible masters bus devices t I2CR ...
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... Min Max 0.5 × 0 0.3 × OV (max) -0.5 DD 0.9 × OV — DD 0.1 × OV — DD — ±10 DD Table 1 and Table 2. Min Max Unit — 6 — ns — 3.0 — ns 0.3 — ns symbolizes PCI timing PCIVKH SYS Freescale Semiconductor Unit μA Notes for , reference ...
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... PCIXKH Figure 36 provides the AC test load for PCI. Output Figure 37 shows the PCI input AC timing conditions. CLK Input Figure 37. PCI Input AC Timing Measurement Conditions MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor 1 Symbol t PCKHOV t PCKHOX t PCKHOZ t ...
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... MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev PCKHOV t PCKHOX t PCKHOZ Symbol Condition – — — ≤ V ≤ Symbol ns to ensure proper operation. TIWID Min Max Unit 2.4 — V — 0.5 V — 0 –0.3 0.8 V μA — ± Typ Unit TIWID Freescale Semiconductor ...
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... GPIO inputs and outputs are asynchronous to any visible clock. GPIO outputs should be synchronized before use by any external synchronous logic. GPIO inputs are required to be valid for at least t MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor = 50 Ω Ω ...
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... Table 53. IPIC DC Electrical Characteristics Symbol Condition V — — — 6 3 not relevant for those pins Ω Min Max 2 0.3 DD –0.3 0.8 — ±10 — 0.5 — 0 Symbol Min t 20 PIWID ns to ensure proper operation when working PIWID Freescale Semiconductor Unit V V μ Unit ns ...
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... Figure 41 provides the AC test load for the SPI. Output MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor Table 55. SPI DC Electrical Characteristics Symbol Condition –6.0 mA ...
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... Output low voltage Input high voltage MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev Table 56. Note that although the specifications t NEIXKH t NEKHOV t NIIXKH t NIIVKH t NIKHOV Symbol Condition –2 3 — IH Min Max Unit 2.4 — V — 0 Freescale Semiconductor ...
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... Output Figure 45 represents the AC timing from reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge is the active edge. MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor Symbol Condition V — ≤ V ≤ ...
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... OL V — — ≤ V ≤ Symbol Min t 0 UIKHOV t 1 UEKHOV t 0 UIKHOX t 1 UEKHOX Min Max Unit 2.4 — V — 0 –0.3 0.8 V μA — ±10 1 Max Unit Notes 11.5 ns — 11.6 ns — 8.0 ns — 10.0 ns — Freescale Semiconductor ...
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... Figure 47 shows the UTOPIA timing with external clock. UtopiaCLK (Input) t UEIVKH Input Signals: UTOPIA Output Signals: UTOPIA Figure 47. UTOPIA AC Timing (External Clock) Diagram MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor 2 Symbol t UIIVKH t UEIVKH t UIIXKH t UEIXKH (first two letters of functional block)(signal)(state)(reference)(state) for outputs ...
Page 64
... Input low voltage Input current MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev UIIXKH t UIIVKH t UIKHOV t UIKHOX Symbol Condition –2 3 — — ≤ V ≤ Min Max 2.4 — — 0.5 2 0.3 DD –0.3 0.8 — ±10 DD Freescale Semiconductor Unit μA ...
Page 65
... The symbols used for timing specifications follow the pattern of t inputs and t (first two letters of functional block)(reference)(state)(signal)(state) internal timing (HI) for the time t serial MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor HDLC, BISYNC, Transparent, and Synchronous UART Symbol t HIKHOV t ...
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... Note: The clock edge is selectable. Figure 51. AC Timing (Internal Clock) Diagram MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev Ω Figure 49. AC Test Load Table 62 and t HEIXKH t HEKHOV t HEKHOX t HIIXKH t HIIVKH tHIKHOV t HIKHOX Ω L Table 63. Note that although the Freescale Semiconductor ...
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... USB receive signals skew (RS) among RXP, RXN, and RXD (PND). Also, t transmit signals skew (TS) between TXP and TXN (PN). 2.Skew measurements are done at OV Figure 52 provide the AC test load for the USB. Output MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor Table 64. USB DC Electrical Characteristics Symbol Table 65 ...
Page 68
... MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev Section 21.1, “Package Parameters for the TBGA Package,” for information on the package. 37.5 mm × 37.5 mm 740 1. Sn/36 Pb/2 Ag (ZU package) 95.5 Sn/0.5 Cu/4Ag (VV package) 0.64 mm Freescale Semiconductor ...
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... Mechanical Dimensions of the TBGA Package Figure 53 depicts the mechanical dimensions and bottom surface nomenclature of the device, 740-TBGA package. Figure 53. Mechanical Dimensions and Bottom Surface Nomenclature of the TBGA Package MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor Package and Pin Listings 69 ...
Page 70
... AG33, AJ36 AT1, AK2 AT26 AT29 AT24 AU27, AT27 Power Pin Type Notes Supply I/O GV — DD I/O GV — DD I/O GV — DD I/O GV — DD I/O GV — — — — DD I/O GV — DD I/O GV — DD I/O GV — — — — — — — — DD Freescale Semiconductor ...
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... PCI_AD[29:25]/CE_PG[29:25] PCI_AD[24]/CE_PG[24] PCI_AD[23:0]/CE_PG[23:0] PCI_C/BE[3:0]/CE_PF[10:7] PCI_PAR/CE_PF[11] PCI_FRAME/CE_PF[12] PCI_TRDY/CE_PF[13] MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor Package Pin Number AU8, AU7 AL32, AU33 AK37, AT37 AN1, AR2 AN25, AK1 AL37, AT36 AP2, AT2 ...
Page 72
... DD I — — — — — DD I/O OV — DD I/O OV — DD I/O OV — DD I/O OV — DD I/O OV — DD I/O OV — — — — — — DD I/O OV — DD I/O OV — — DD I/O OV — DD I/O OV — DD I/O OV — — DD Freescale Semiconductor ...
Page 73
... M2SRCID[3]/LSRCID[3] IIC1_SDA IIC1_SCL IIC2_SDA IIC2_SCL CE_PA[0] CE_PA[1:2] CE_PA[3:7] CE_PA[8] CE_PA[9:12] CE_PA[13:14] CE_PA[15] MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor Package Pin Number J33 J34 G37 F34 G35 Programmable Interrupt Controller E34 C37 F35 F36 H34 ...
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... DD I — DD I/O OV — — DD I/O OV — — DD I/O OV — DD I/O OV — — DD I/O OV — — — DD I/O OV — DD I/O OV — DD I/O OV — DD I/O OV — — DD I/O OV — — — — Freescale Semiconductor ...
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... THERM0 THERM1 GND GV DD MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor Package Pin Number L35 AU34 PMC B36 System Control L37 L36 M33 Thermal Management AP19 AT31 Power and Ground Signals K35 K36 AM29 K37 ...
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... Power for UCC2 Ethernet interface option 1 (2.5 V, 3.3 V) Power for UCC2 Ethernet interface option 2 (2.5 V, 3.3 V) Power for V — DD core (1.2 V) PCI, OV — DD 10/100 Ethernet, and other standard (3 DDR — reference voltage I DDR — reference voltage I — — — Freescale Semiconductor ...
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... MEMC_MECC[6:7] MEMC_MDM[0:8] MEMC_MDQS[0:8] MEMC_MBA[0:1] MEMC_MBA[2] MEMC_MA[0:14] MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor Package Pin Number No Connect AM20, AU19 Table 67. MPC8358E TBGA Pinout Listing Package Pin Number DDR SDRAM Memory Controller Interface AJ34, AK33, AL33, AL35, AJ33, AK34, AK32, ...
Page 78
... Notes Supply — — — — — — — — DD I/O OV — — DD I/O OV — DD I/O OV — DD I/O OV — I/O OV — — — — — — DD Freescale Semiconductor ...
Page 79
... LSYNC_OUT LSYNC_IN MCP_OUT IRQ0/MCP_IN IRQ[1]/M1SRCID[4]/M2SRCID[4]/ LSRCID[4] MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor Package Pin Number C20 D36 B37 Local Bus Controller Interface N32, N33, N35, N36, P37, P32, P34, R36, R35, R34, R33, T37, T35, T34, T33, U37, T32, U36, U34, ...
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... DD I/O OV — DD I/O OV — — I/O LV — DD0 I/O OV — — DD I/O OV — — DD I/O OV — — DD I/O OV — — DD I/O OV — — DD I/O OV — — DD I/O OV — — DD Freescale Semiconductor ...
Page 81
... TEST TEST_SEL QUIESCE MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor Package Pin Number AE2, AE1, AD5, AD3, AD2, AC6, AC5, AC4, AC2, AC1, AB5, AB4, AB3, AB1, AA6, AA4, AA2, Y6, Y4, Y3, Y2, Y1, W6, W5, W2, V5, V3, V2 ...
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... AV 2 — PLL (1.2 V) Power for AV 5 — DD e300 PLL (1.2 V) Power for AV 6 — DD system PLL (1.2 V) — — — Power for GV — DD DDR DRAM I/O voltage (2.5 or 1.8 V) Power for LV 0 — DD UCC1 Ethernet interface (2.5 V, 3.3 V) Freescale Semiconductor ...
Page 83
... SPARE1 SPARE3 SPARE4 SPARE5 MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor Package Pin Number C17, D16 B18, E21 C36, D29, D35, E16, F9, F12, F15, F17, F18, F20, F21, F23, F25, F26, F29, F31, F32, F33, G6, J6, ...
Page 84
... AM16, AM17, AM20, AN13, AN16, AN17, AP10, AP11, AP13, AP15, AP18, AR11, AR13, AR14, AR15, AR16, AR17, AR20, AT11, AT12, AT13, AT14, AT16, AT17, AT18, AU10, AU11, AU12, AU13, AU15, AU19 . DD Power Pin Type Notes Supply — — — DD Freescale Semiconductor ...
Page 85
... MPC8360E. MPC8360E ce_clk to QUICC Engine Block QUICC Engine PLL CFG_CLKIN_DIV CLKIN MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor e300 Core Core PLL csb_clk DDRC1 ddr1_clk DDRC2 Clock Unit ...
Page 86
... Core PLL csb_clk DDRC ddr1_clk Clock Unit System lb_clk PLL /n LBIU DLL csb_clk to Rest of the Device PCI Clock Divider Figure 55. MPC8358E Clock Subsystem core_clk MEMC1_MCK[0:5] MEMC1_MCK[0:5] /2 LCLK[0:2] Local Bus LSYNC_OUT Memory Device LSYNC_IN PCI_CLK/ PCI_SYNC_IN PCI_SYNC_OUT PCI_CLK_OUT[0:2] Freescale Semiconductor DDRC Memory Device ...
Page 87
... Note that lb_clk is not the external local bus or DDRC2 frequency; lb_clk passes through the a LB clock divider to create the external local bus clock outputs (LSYNC_OUT and LCLK[0:2]). The LB clock divider ratio is controlled by LCRR[CLKDIV]. MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor 55, the primary clock input (frequency) is multiplied by the QUICC Clocking 87 ...
Page 88
... DD Options 1 csb_clk , csb_clk /2, /3 csb_clk Section 25.1, “Part Numbers Fully 2 533 MHz 667 MHz 266–533 266–667 133–333 266–500 100–166.67 16.67–133 25–66.67 133 166 Freescale Semiconductor Unit MHz MHz MHz MHz MHz MHz MHz ...
Page 89
... The RCWL[SVCOD] denotes the system PLL VCO internal frequency as shown in The VCO divider must be set properly so that the system VCO frequency is in the range of 600–1400 MHz. MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor Table 70. System PLL Multiplication Factors System PLL RCWL[SPMF] ...
Page 90
... Table 72 2 Input Clock Frequency (MHz) 25 33.33 66.67 csb_clk Frequency (MHz) 133 100 200 100 133 266 125 166 333 150 200 175 233 200 266 225 300 250 333 275 300 325 133 100 200 133 266 166 333 Freescale Semiconductor ...
Page 91
... Table 73 in Table 73 should be considered reserved. RCWL[COREPLL] 0– MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor csb_clk : 2 Input Clock Ratio 6:1 7:1 8:1 9:1 10:1 11:1 12:1 13:1 14:1 15:1 16:1 shows the encodings for RCWL[COREPLL]. COREPLL values not listed Table 73 ...
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... NOTE Table 74 shows the multiplication factor encodings for the QUICC Engine QUICC Engine PLL Multiplication Factor = RCWL[CEPMF RCWL[CEPDF VCO divider ÷ 8 ÷ 2 ÷ 4 ÷ 8 ÷ 8 ÷ 2 ÷ 4 ÷ 8 ÷ 8 ÷ 2 ÷ 4 ÷ 8 ÷ 8 × 16 Reserved × 2 × 3 × 4 Freescale Semiconductor ...
Page 93
... MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor QUICC Engine PLL Multiplication Factor = RCWL[CEPMF RCWL[CEPDF]) 0 × × × × × × × ...
Page 94
... MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev QUICC Engine PLL Multiplication Factor = RCWL[CEPMF RCWL[CEPDF]) 1 × 5.5 1 × 6.5 1 × 7.5 1 × 8.5 1 × 9.5 1 × 10.5 1 × 11.5 1 × 12.5 1 × 13.5 1 × 14.5 RCWL[CEVCOD] VCO Divider Reserved NOTE Freescale Semiconductor ...
Page 95
... MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor shows suggested PLL configurations for 33 and 66 MHz input clocks and for the appropriate operating frequencies for your Table 76. Suggested PLL Configurations Input CSB Freq ...
Page 96
... Copy the CEPMF and CEPDF Freescale Semiconductor 667 (MHz) ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ...
Page 97
... Junction-to-ambient (@ 1 m/s) on four-layer board (2s2p) Junction-to-ambient (@ 2 m/s) on single-layer board (1s) Junction-to-ambient (@ 2 m/s) on four-layer board (2s2p) Junction-to-board thermal Junction-to-case thermal MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor Example 1. Sample Table Use Input Clock CSB Freq (MHz) (MHz) ...
Page 98
... MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev × where P is the power dissipation of the I/O drivers I/O I/O , can be obtained from the equation Symbol Value Unit Notes ψ °C – are possible Freescale Semiconductor 6 ...
Page 99
... When a heat sink is used, the thermal resistance is expressed as the sum of a junction to case thermal resistance and a case to ambient thermal resistance θ θ θ where junction-to-ambient thermal resistance (°C/W) θ JA MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor ) D ) can be used to determine the junction temperature with Thermal 99 ...
Page 100
... For instance, the user can change the size of the heat θ CA Airflow Natural convention 1 m/s 2 m/s Natural convention 1 m/s 2 m/s Natural convention 1 m/s 2 m/s Natural convention 1 m/s 2 m/s 1 m/s 35 × TBGA Junction-to-Ambient Thermal Resistance 10.7 6.2 5.3 8.1 4.4 3.7 5.4 3.2 2.4 6.4 3.8 2.5 2.8 Freescale Semiconductor ...
Page 101
... Dow-Corning Corporation Dow-Corning Electronic Materials 2200 W. Salzburg Rd. Midland, MI 48686-0997 Internet: www.dowcorning.com Shin-Etsu MicroSi, Inc. 10028 S. 51st St. Phoenix, AZ 85044 Internet: www.microsi.com MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor 603-224-9988 408-749-7601 818-842-7277 408-436-8770 800-522-6752 603-635-5102 781-935-4850 800-248-2481 888-642-7674 ...
Page 102
... D 24 System Design Information This section provides electrical and thermal design recommendations for successful application of the MPC8360E/58E. Additional information can be found in MPC8360E/MPC8358E PowerQUICC Design Checklist (AN3097). MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 102 800-347-4572 ) D Freescale Semiconductor ...
Page 103
... V decoupling capacitors should receive their power from separate V MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor 1) generates the platform clock from the externally supplied CLKIN Section 22.1, “System PLL Configuration.” ...
Page 104
... MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 104 , and LV planes, to enable quick recharging of the smaller chip C). is trimmed until the voltage at the pad equals P )/ required. Unused active high and GND pins (see Figure 57). The DD and R are designed to be close to each P N Freescale Semiconductor DD ...
Page 105
... HRESET is asserted, is latched when HRESET deasserts, at which time the input receiver is disabled and the I/O circuit takes on its normal function. Careful board layout with stubless connections to these MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor OV R ...
Page 106
... AL = 667 MHz for more information on available package types QUICC Platform Engine 3 Frequency Revision Frequency D = 266 MHz E = 300 MHz A = rev. 2 400 MHz D = 266 MHz G = 400 MHz A = rev. 2 333 MHz H = 500 MHz F = 333 MHz G = 400 MHz H = 500 MHz Freescale Semiconductor A Die silicon silicon — ...
Page 107
... CLKIN/2 is driven out on the PCI_CLK_OUTn signals.” • In Section 22.1, “System PLL • In Table 80, added extended temperature characteristics. 2 12/2007 Initial release. MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor Table 81. SVR Settings SVR Package (Rev. 2.0) TBGA 0x8048_0020 TBGA 0x8049_0020 ...
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... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...