sc16c652b NXP Semiconductors, sc16c652b Datasheet
sc16c652b
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sc16c652b Summary of contents
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... An internal loop-back capability allows on-board diagnostics. Independent programmable baud rate generators are provided to select transmit and receive baud rates. The SC16C652B operates 3.3 V and 2.5 V and the industrial temperature range, and is available in plastic LQFP48 and very small (Micro-UART) HVQFN32 packages. 2. Features 2 channel UART ...
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... Description plastic low profile quad flat package; 48 leads; body 7 plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 5 5 0.85 mm Rev. 04 — 1 September 2005 SC16C652B Version 7 1.4 mm SOT313-2 SOT617-1 © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... CONTROL RESET REGISTER CSA SELECT CSB INTA, INTB INTERRUPT TXRDYA, TXRDYB CONTROL RXRDYA, RXRDYB Fig 1. Block diagram of SC16C652B SC16C652B_4 Product data sheet Dual UART with 32-byte FIFOs and IrDA encoder/decoder AND LOGIC LOGIC CLOCK AND BAUD RATE GENERATOR LOGIC XTAL1 Rev. 04 — ...
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... TXB 8 OP2B 9 10 CSA 11 CSB n.c. 12 terminal 1 index area RXB 4 RXA SC16C652BIBS TXA 5 TXB 6 7 OP2B CSA 8 Transparent top view Rev. 04 — 1 September 2005 SC16C652B 36 RESET 35 DTRB 34 DTRA 33 RTSA 32 OP2A 31 RXRDYA 30 INTA 29 INTB n.c. 002aaa593 24 RESET 23 RTSA 22 OP2A ...
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... O Data Terminal Ready (active LOW). These outputs are associated with individual UART channels, A through B. A logic 0 on this pin indicates that the SC16C652B is powered-on and ready. This pin can be controlled via the modem control register. Writing a logic 1 to MCR[0] will set the DTR output to logic 0, enabling the modem. ...
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... O Transmit data A, B. These outputs are associated with individual serial transmit channel data from the SC16C652B. The TX signal will be a logic 1 during reset, idle (no data), or when the transmitter is disabled. During the local loop-back mode, the TX output pin is disabled and TX data is internally connected to the UART RX input ...
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... The FIFO memory greatly reduces the bandwidth requirement of the external controlling CPU, increases performance, and reduces power consumption. The SC16C652B is capable of operation Mbit/s with a 80 MHz clock. With a crystal or external clock input of 7.3728 MHz, the user can select data rates up to 460.8 kbit/s. ...
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... UART A-B functions The UART provides the user with the capability to bi-directionally transfer information between an external CPU, the SC16C652B package, and an external serial device. A logic 0 on chip select pins CSA and/or CSB allows the user to configure, send data, and/or receive data via UART channels A-B. Individual channel select functions are shown ...
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... Automatic hardware flow control is selected by setting EFR[6] (RTS) and EFR[7] (CTS logic 1. If CTS transitions from a logic logic 1 indicating a flow control request, ISR[5] will be set to a logic 1 (if enabled via IER[7:6]), and the SC16C652B will suspend TX transmissions as soon as the stop bit of the character in process is shifted out. ...
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... Hardware/software and time-out interrupts The interrupts are enabled by IER[3:0]. Care must be taken when handling these interrupts. Following a reset, if Interrupt Enable Register (IER) bit the SC16C652B will issue a Transmit Holding Register interrupt. This interrupt must be serviced prior to continuing operations. The ISR provides the current singular highest priority interrupt only. ...
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... TX/RX channel control. The programmable Baud Rate Generator is capable of operating with a frequency MHz. To obtain maximum data rate necessary to use full rail swing on the clock input. The SC16C652B can be configured for internal or external clock operation. For internal clock oscillator operation, an industry standard microprocessor crystal is connected externally between the XTAL1 and XTAL2 pins ...
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... DMA operation The SC16C652B FIFO trigger level provides additional flexibility to the user for block mode operation. The user can optionally operate the transmit and receive FIFOs in the DMA mode (FCR[3]). The DMA mode affects the state of the RXRDY and TXRDY output pins ...
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... RECEIVE FIFO SHIFT REGISTERS REGISTER FLOW CONTROL LOGIC CONTROL CLOCK AND BAUD RATE GENERATOR XTAL1 XTAL2 Rev. 04 — 1 September 2005 SC16C652B TXA, TXB IR ENCODER RXA, RXB IR DECODER RTSA, RTSB CTSA, CTSB DTRA, DTRB MODEM DSRA, DSRB LOGIC (OP1A, OP1B) RIA, RIB ...
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... Philips Semiconductors 6.11 Sleep mode Sleep mode is an enhanced feature of the SC16C652B UART enabled when EFR[4], the enhanced functions bit, is set and when IER[4] of both channels are set. Sleep mode is entered when: • Modem input pins are not toggling. • The serial data input line, RX, is idle (logic HIGH). ...
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... Enhanced Feature Register, Xon1/Xon2 and Xoff1/Xoff2 are accessible only when LCR is set to ‘BFh’. SC16C652B_4 Product data sheet Dual UART with 32-byte FIFOs and IrDA encoder/decoder details the assigned bit functions for the SC16C652B internal registers. The [1] Bit 7 Bit 6 Bit 5 bit 7 ...
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... CTS pin transitions from a logic logic 1. RTS interrupt. logic 0 = disable the RTS interrupt (normal default condition) logic 1 = enable the RTS interrupt. The SC16C652B issues an interrupt when the RTS pin transitions from a logic logic 1. Xoff interrupt. logic 0 = disable the software flow control, receive Xoff interrupt (normal default condition) logic 1 = enable the software fl ...
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... ISR loading the THR with new data characters. 7.2.2 IER versus Receive/Transmit FIFO polled mode operation When FCR[0] = logic 1, resetting IER[3:0] enables the SC16C652B in the FIFO polled mode of operation. In this mode, interrupts are not generated and the user must poll the LSR register for TX and/or RX data status ...
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... Once active, the TXRDY pin will logic 1 after the first character is loaded into the transmit holding register. Receive operation in mode ‘0’: When the SC16C652B is in 16C450 mode the FIFO mode (FCR[0] = logic 1; FCR[3] = logic 0) and there is at least one character in the receive FIFO, the RXRDY pin will be a logic 0 ...
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... FIFO is completely full. It will be a logic 0 when the trigger level has been reached. Receive operation in mode ‘1’: When the SC16C652B is in FIFO mode (FCR[0] = logic 1; FCR[3] = logic 1) and the trigger level has been reached Receive Time-Out has occurred, the RXRDY pin will logic 0. ...
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... Philips Semiconductors 7.4 Interrupt Status Register (ISR) The SC16C652B provides six levels of prioritized interrupts to minimize external software interaction. The Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the ISR will provide the user with the highest pending interrupt level to be serviced ...
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... Word length (bits) Stop bit length (bit times LCR[1:0] word length LCR[0] Word length (bits Rev. 04 — 1 September 2005 SC16C652B Table 17). Table 18). Table 19). © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... INT (A, B) outputs to the active mode and sets OP2 to a logic 0 MCR[2] (OP1). OP1A/OP1B are not available as an external signal in the SC16C652B. This bit is instead used in the Loop-back mode only. In the Loop-back mode, this bit is used to write the state of the modem RI interface signal. MCR[1] ...
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... Philips Semiconductors 7.7 Line Status Register (LSR) This register provides the status of data transfers between the SC16C652B and the CPU. Table 21: Bit Symbol 7 LSR[7] 6 LSR[6] 5 LSR[5] 4 LSR[4] 3 LSR[3] 2 LSR[2] 1 LSR[1] 0 LSR[0] SC16C652B_4 Product data sheet Dual UART with 32-byte FIFOs and IrDA encoder/decoder ...
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... A modem Status Interrupt will be generated. [1] MSR[2] RI logic change (normal default condition) logic 1 = the RI input to the SC16C652B has changed from a logic logic 1. A modem Status Interrupt will be generated. [1] MSR[1] DSR logic DSR change (normal default condition) logic 1 = the DSR input to the SC16C652B has changed state since the last time it was read ...
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... Special Character Detect. logic 0 = special character detect disabled (normal default condition) logic 1 = special character detect enabled. The SC16C652B compares each incoming receive character with Xoff2 data match exists, the received data will be transferred to FIFO and ISR[4] will be set to indicate detection of special character. Bit-0 in the X-registers corresponds with the LSB bit for the receive character. When this feature is enabled, the normal software fl ...
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... Philips Semiconductors Table 24: Cont [1] When using a software flow control the Xon/Xoff characters cannot be used for data transfer. 7.11 SC16C652B external reset condition Table 25: Register IER FCR ISR LCR MCR LSR MSR SPR DLL DLM Table 26: Output TXA, TXB ...
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... (other outputs (databus (other outputs 800 A 1.85 OH (data bus 400 A 1.85 OH (other outputs MHz - [ Rev. 04 — 1 September 2005 SC16C652B Min Max - 7 GND 0 0 +85 65 +150 - 500 = 2 3 Max Min Max Min 0.45 0.3 0.6 0.5 V 2 ...
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... RCLK 25 pF load - 100 - 100 [3] 8T 24T RCLK - 100 [ RCLK - 100 - 100 Rev. 04 — 1 September 2005 SC16C652B Min Max Min ...
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... Min [3] - 200 valid address t 13h active t t 13d 15d t 13w active t 16h t 16s data Rev. 04 — 1 September 2005 SC16C652B Max Min Max Min RCLK RCLK - © Koninklijke Philips Electronics N.V. 2005. All rights reserved. ...
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... Rev. 04 — 1 September 2005 SC16C652B 002aaa110 change of state t 18d active active t 19d active active t 18d change of state 002aaa352 © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... data bits 6 data bits 7 data bits 16 baud rate clock Rev. 04 — 1 September 2005 SC16C652B next data parity stop start bit bit bit 20d active t 21d active 002aaa113 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. ...
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... Dual UART with 32-byte FIFOs and IrDA encoder/decoder start bit data bits ( start bit data bits ( Rev. 04 — 1 September 2005 SC16C652B next data parity stop start bit bit bit 25d active data ready t 26d ...
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... 28d transmitter not ready Rev. 04 — 1 September 2005 SC16C652B next data parity stop start bit bit bit 24d active 002aaa116 next data parity stop ...
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... Dual UART with 32-byte FIFOs and IrDA encoder/decoder start bit data bits ( data bits 6 data bits 7 data bits t 28d t 27d FIFO full Rev. 04 — 1 September 2005 SC16C652B parity stop bit bit 002aab065 © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... Dual UART with 32-byte FIFOs and IrDA encoder/decoder UART frame start bit time bit time start Rev. 04 — 1 September 2005 SC16C652B data bits bit time clock delay data bits UART frame © ...
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... 2.5 scale (1) ( 0.27 0.18 7.1 7.1 9.15 9.15 0.5 0.17 0.12 6.9 6.9 8.85 8.85 REFERENCES JEDEC JEITA MS-026 Rev. 04 — 1 September 2005 SC16C652B detail 0.75 0.95 1 0.2 0.12 0.1 0.45 0.55 EUROPEAN PROJECTION © Koninklijke Philips Electronics N.V. 2005. All rights reserved. SOT313 ...
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... 2.5 scale (1) ( 5.1 3.25 5.1 3.25 0.5 3.5 4.9 2.95 4.9 2.95 REFERENCES JEDEC JEITA MO-220 - - - Rev. 04 — 1 September 2005 SC16C652B detail 0.5 0.05 0.1 3.5 0.1 0.05 0.3 EUROPEAN PROJECTION © Koninklijke Philips Electronics N.V. 2005. All rights reserved. SOT617 ISSUE DATE ...
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... SC16C652B_4 Product data sheet Dual UART with 32-byte FIFOs and IrDA encoder/decoder 2 called small/thin packages. Rev. 04 — 1 September 2005 SC16C652B 3 350 mm so called © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... LBGA, LFBGA, SQFP, [3] , TFBGA, VFBGA, XSON , SO, SOJ [8] [9] [8] , PMFP , WQCCN.. measured in the atmosphere of the reflow oven. The package Rev. 04 — 1 September 2005 SC16C652B Soldering method Wave Reflow not suitable suitable [4] not suitable suitable suitable suitable [5] [6] not recommended suitable ...
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... Product data sheet Dual UART with 32-byte FIFOs and IrDA encoder/decoder Abbreviations Description First In, First Out Universal Asynchronous Receiver/Transmitter Central Processing Unit Integrated Service Digital Network Direct Memory Access Rev. 04 — 1 September 2005 SC16C652B © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... Section 6.8 “Programmable baud rate generator” on page “... from • Table 6 on page • Add new • Table 9 “SC16C652B internal registers” on page and references previously shaded table cells • Table 18 “LCR[2] stop bit length” on page • Table 19 “LCR[1:0] word length” on page • ...
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... Trademarks Notice — All referenced brands, product names, service names and trademarks are the property of their respective owners. Rev. 04 — 1 September 2005 SC16C652B © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... Line Control Register (LCR 7.6 Modem Control Register (MCR 7.7 Line Status Register (LSR 7.8 Modem Status Register (MSR 7.9 Scratchpad Register (SPR 7.10 Enhanced Feature Register (EFR 7.11 SC16C652B external reset condition . . . . . . . 26 8 Limiting values Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . 28 10.1 Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . 29 11 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 36 12 Soldering ...