SSTUH32866 Philips Semiconductors, SSTUH32866 Datasheet
SSTUH32866
Related parts for SSTUH32866
SSTUH32866 Summary of contents
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... Rev. 01 — 13 May 2005 1. General description The SSTUH32866 is a 1.8 V configurable register specifically designed for use on DDR2 memory modules requiring a parity checking function defined in accordance with the JEDEC JESD82-7 standard for the SSTU32864 registered buffer, while adding the parity checking function in a compatible pinout. The JEDEC standard for SSTUH32866 is pending publication. The register is confi ...
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... LFBGA96 plastic low profile fine-pitch ball grid array package; 96 balls; body 13.5 5.5 Rev. 01 — 13 May 2005 SSTUH32866 www.DataSheet4U.com Version SOT536-1 1.05 mm SOT536-1 1.05 mm © Koninklijke Philips Electronics N.V. 2005. All rights reserved. ...
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... Philips Semiconductors 5. Functional diagram (1) Disabled configuration. Fig 1. Functional diagram of SSTUH32866 Register A configuration with and (positive logic) 9397 750 14199 Product data sheet 1.8 V high-drive DDR2 configurable registered buffer with parity RESET CK CK VREF DCKE DODT ...
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... D8 to D14 PARITY CHECK CLK CLK CLK 2-BIT LPS1 COUNTER (internal node) R Rev. 01 — 13 May 2005 SSTUH32866 www.DataSheet4U.com Q2A, Q3A, Q5A, Q6A, 11 D2, D3, D5, D6, Q8A to Q14A D8 to D14 11 11 Q2B, Q3B, Q5B, Q6B, Q8B to Q14B 1 PPO 0 D CLK R ...
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... GND GND N D11 D22 D12 D23 GND GND R D13 D24 D14 D25 VREF V DD Rev. 01 — 13 May 2005 SSTUH32866 www.DataSheet4U.com 5 6 QCKE DNU Q2 Q15 Q3 Q16 QODT DNU Q5 Q17 Q6 Q18 C1 C0 QCS DNU n.c. n.c. Q8 Q19 Q9 Q20 Q10 Q21 Q11 ...
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... DODT DNU D12 DNU GND GND R D13 DNU DCKE DNU VREF V DD Rev. 01 — 13 May 2005 SSTUH32866 www.DataSheet4U.com 5 6 QCKEA QCKEB Q2A Q2B Q3A Q3B QODTA QODTB Q5A Q5B Q6A Q6B C1 C0 QCSA QCSB n.c. n.c. Q8A Q8B Q9A ...
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... V CMOS output [1] 1.8 V CMOS output [1] 1.8 V CMOS output Rev. 01 — 13 May 2005 SSTUH32866 www.DataSheet4U.com Description ground power supply voltage input reference voltage positive master clock input negative master clock input Configuration control inputs; Register A or Register B and mode mode select ...
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... Data outputs = Q10, Q12, Q13 when and Functional description The SSTUH32866 is a 25-bit 14-bit configurable registered buffer with parity, designed for 1 1 All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control and reset (RESET) inputs are LVCMOS ...
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... As long as the data inputs are LOW, and the clock is stable during the time from the LOW-to-HIGH transition of RESET until the input receivers are fully enabled, the design of the SSTUH32866 must ensure that the outputs will remain LOW, thus ensuring no glitches on the output. ...
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... X or floating X or floating = LOW-to-HIGH transition; Inputs inputs = H (D1 to D25) even even even even floating is the previous state of output QERR. 0 Rev. 01 — 13 May 2005 SSTUH32866 www.DataSheet4U.com = HIGH-to-LOW transition [1] Outputs Qn QCS ...
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... CSR, - and PAR_IN inputs data (Dn), CSR 0.125 ref and PAR_IN inputs data (Dn), CSR, - and PAR_IN inputs [1] RESET [1] RESET [2] CK, CK 0.675 [2] CK, CK 600 Rev. 01 — 13 May 2005 SSTUH32866 www.DataSheet4U.com Min Max Unit 0.5 +2.5 V [1] [2] 0.5 +2.5 V [1] [ ...
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... mA 1 250 mV 1 ref 0 600 mV; ICR i(p- 1 GND 1 Rev. 01 — 13 May 2005 SSTUH32866 www.DataSheet4U.com Typ Max Unit - +70 C Min Typ Max Unit 1 0 ...
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... CK and CK to QERR from CK and from RESET to Qn from RESET to PPO from RESET to QERR Table 6), unless otherwise specified. See Conditions from from from Rev. 01 — 13 May 2005 SSTUH32866 www.DataSheet4U.com Figure 2. Min Typ Max Unit - - 450 MHz 1 ...
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... D25 Q25 PAR_IN PPO QERR Fig 7. Timing diagram for SSTUH32866 used as a single device 9397 750 14199 Product data sheet 1.8 V high-drive DDR2 configurable registered buffer with parity ...
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... Q14 PAR_IN PPO QERR (not used) Fig 8. Timing diagram for the first SSTUH32866 ( Register A configuration) device used in pair 9397 750 14199 Product data sheet 1.8 V high-drive DDR2 configurable registered buffer with parity ...
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... PPO (not used) QERR (1) PAR_IN is driven from PPO of the first SSTUH32866 device. Fig 9. Timing diagram for the second SSTUH32866 ( Register B configuration) device used in pair 9397 750 14199 Product data sheet 1.8 V high-drive DDR2 configurable registered buffer with parity ...
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... V input V ICR = 600 250 mV (AC voltage levels) for differential inputs. V ref = V 250 mV (AC voltage levels) for differential inputs. V ref Rev. 01 — 13 May 2005 SSTUH32866 www.DataSheet4U.com 20 %, unless otherwise specified 350 ps OUT (1) C ...
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... PD LVCMOS RESET output and t are the same PHL 250 mV (AC voltage levels) for differential inputs. V ref = V 250 mV (AC voltage levels) for differential inputs. V ref Rev. 01 — 13 May 2005 SSTUH32866 www.DataSheet4U.com V V ICR ref V IL 002aaa374 = V for LVCMOS inputs. ...
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... V/ns 0 DUT OUT includes probe and jig capacitance. output dv_f DUT OUT includes probe and jig capacitance. dt_r dv_r 20 % output Rev. 01 — 13 May 2005 SSTUH32866 www.DataSheet4U.com 20 %, unless otherwise specified test point ( 002aab117 ...
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... LVCMOS RESET PLH 0.15 V output waveform 2 timing V ICR inputs t HL output V CC waveform 1 Rev. 01 — 13 May 2005 SSTUH32866 www.DataSheet4U.com 20 %, unless otherwise specified test point ( 002aaa500 002aaa501 V ...
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... L includes probe and jig capacitance ICR CK t PLH output = and t are the same PHL PD = 600 mV Rev. 01 — 13 May 2005 SSTUH32866 www.DataSheet4U.com V V i(p-p) ICR 002aaa503 20 %, unless otherwise specified. test point ( 002aaa654 V V ICR ...
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... RESET output = and t are the same PHL 250 mV (AC voltage levels) for differential inputs. V ref = V 250 mV (AC voltage levels) for differential inputs. V ref Rev. 01 — 13 May 2005 SSTUH32866 www.DataSheet4U.com PHL 002aaa376 = V for LVCMOS inputs ...
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... 13 0.8 0.15 0.1 13.4 REFERENCES JEDEC JEITA Rev. 01 — 13 May 2005 SSTUH32866 www.DataSheet4U.com detail 0.1 0.2 EUROPEAN ISSUE DATE PROJECTION 00-03-04 03-02-05 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. SOT536 ...
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... Product data sheet 1.8 V high-drive DDR2 configurable registered buffer with parity 2 called small/thin packages. Rev. 01 — 13 May 2005 SSTUH32866 www.DataSheet4U.com 3 350 mm so called © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... Suitability of surface mount IC packages for wave and reflow soldering methods [3] , LBGA, LFBGA, SQFP, , TFBGA, VFBGA, XSON [8] [9] [8] , PMFP , WQCCN.. measured in the atmosphere of the reflow oven. The package Rev. 01 — 13 May 2005 SSTUH32866 www.DataSheet4U.com Soldering method Wave Reflow not suitable suitable [4] not suitable suitable suitable ...
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... Pulse Repetition Rate Registered Dual In-line Memory Module Stub Series Terminated Logic Data sheet status Change notice Product data sheet - Rev. 01 — 13 May 2005 SSTUH32866 www.DataSheet4U.com Doc. number Supersedes 9397 750 14199 - © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... Trademarks Notice — All referenced brands, product names, service names and trademarks are the property of their respective owners. Rev. 01 — 13 May 2005 SSTUH32866 www.DataSheet4U.com © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Published in The Netherlands SSTUH32866 www.DataSheet4U.com Date of release: 13 May 2005 Document number: 9397 750 14199 ...