PIC12C508A-04I/P Microchip Technology, PIC12C508A-04I/P Datasheet - Page 13

• Manufacturer Part Number: PIC12C508A-04I/P
• Description: IC MCU OTP 512X12 8DIP
• Manufacturer: Microchip Technology
• Series: PIC® 12Cr

Specifications of PIC12C508A-04I/P

• Program Memory Type: OTP
• Program Memory Size: 768B (512 x 12)
• Package / Case: 8-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Ram Size: 25 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC12C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 25 B
• Maximum Clock Frequency: 4 MHz
• Number Of Programmable I/os: 5
• Number Of Timers: 1
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: DVMCPA, ICE2000
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ISPICR1 - ADAPTER IN-CIRCUIT PROGRAMMINGDVMCPA - KIT DVR BOARD EVAL SYSTEM MXDEV1DVA12XP080 - ADAPTER DEVICE FOR MPLAB-ICEAC124001 - MODULE SKT PROMATEII 8DIP/SOIC
• Eeprom Size: -
• Data Converters: -
• Connectivity: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.0
PIC12C5XX memory is organized into program mem-
ory and data memory. For devices with more than 512
bytes of program memory, a paging scheme is used.
Program memory pages are accessed using one STA-
TUS register bit. For the PIC12C509, PIC12C509A,
PICCR509A and PIC12CE519 with a data memory
register file of more than 32 registers, a banking
scheme is used. Data memory banks are accessed
using the File Select Register (FSR).
4.1
The PIC12C5XX devices have a 12-bit Program
Counter (PC) capable of addressing a 2K x 12
program memory space.
Only the first 512 x 12 (0000h-01FFh) for the
PIC12C508, PIC12C508A and PIC12CE518 and 1K x
12 (0000h-03FFh) for the PIC12C509, PIC12C509A,
PIC12CR509A, and PIC12CE519 are physically
implemented. Refer to Figure 4-1. Accessing a
location above these boundaries will cause a wrap-
around within the first 512 x 12 space (PIC12C508,
PIC12C508A and PIC12CE518) or 1K x 12 space
(PIC12C509,
PIC12CE519). The effective reset vector is at 000h,
(see
PIC12C508A and PIC12CE518) or location 03FFh
(PIC12C509,
PIC12CE519)
calibration value. This value should never be
overwritten.
1999 Microchip Technology Inc.
Figure 4-1).
MEMORY ORGANIZATION
Program Memory Organization
PIC12C509A,
PIC12C509A,
contains the internal clock oscillator
Location
01FFh
PIC12CR509A
PIC12CR509A
(PIC12C508,
and
and
FIGURE 4-1:
Note 1: Address 0000h becomes the
CALL, RETLW
effective reset vector. Location
01FFh (PIC12C508, PIC12C508A,
PIC12CE518) or location 03FFh
(PIC12C509, PIC12C509A,
PIC12CR509A, PIC12CE519) con-
tains the MOVLW XX INTERNAL RC
oscillator calibration value.
PROGRAM MEMORY MAP
AND STACK
Reset Vector (note 1)
On-chip Program
On-chip Program
Stack Level 1
Stack Level 2
1024 Word
PC<11:0>
512 Word
Memory
Memory
PIC12C5XX
12
DS40139E-page 13
7FFh
0000h
01FFh
0200h
03FFh
0400h