PIC16F1937-I/P Microchip Technology, PIC16F1937-I/P Datasheet - Page 503

• Manufacturer Part Number: PIC16F1937-I/P
• Description: IC PIC MCU FLASH 512KX14 40-PDIP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F1937-I/P

• Program Memory Type: FLASH
• Program Memory Size: 14KB (8K x 14)
• Package / Case: 40-DIP (0.600", 15.24mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 32MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 36
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 14x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: EUSART/MI2C/SPI
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 14-ch x 10-bit
• A/d Bit Size: 10 bit
• A/d Channels Available: 14
• Height: 4.95 mm
• Length: 53.21 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1.8 V
• Width: 14.73 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Timing Diagrams and Specifications
Timing Parameter Symbology........................... 391, 423, 455
Timing Requirements
TMR0 Register .................................................................... 39
TMR1H Register ................................................................. 39
TMR1L Register .................................................................. 39
TMR2 Register .............................................................. 39, 47
TRIS .................................................................................. 376
TRISA Register ........................................................... 40, 130
TRISB ............................................................................... 133
TRISB Register ........................................................... 40, 135
TRISC ............................................................................... 137
TRISC Register ........................................................... 40, 138
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First Start Bit Timing ................................................. 268
Full-Bridge PWM Output ........................................... 221
Half-Bridge PWM Output .................................. 219, 225
I
I
I
I
I
INT Pin Interrupt.......................................................... 95
Internal Oscillator Switch Timing................................. 74
LCD Interrupt Timing in Quarter-Duty Cycle Drive.... 354
LCD Sleep Entry/Exit when SLPEN = 1 or CS = 00 . 356
PWM Auto-shutdown ................................................ 224
PWM Direction Change ............................................ 222
PWM Direction Change at Near 100% Duty Cycle ... 223
PWM Output (Active-High)........................................ 217
PWM Output (Active-Low) ........................................ 218
Repeat Start Condition.............................................. 269
Reset Start-up Sequence............................................ 87
Reset, WDT, OST and Power-up Timer ... 395, 427, 459
Send Break Character Sequence ............................. 307
SPI Master Mode (CKE = 1, SMP = 1) ..... 403, 435, 467
SPI Mode (Master Mode).......................................... 241
SPI Slave Mode (CKE = 0) ....................... 404, 436, 468
SPI Slave Mode (CKE = 1) ....................... 404, 436, 468
Synchronous Reception (Master Mode, SREN) ....... 311
Synchronous Transmission....................................... 309
Synchronous Transmission (Through TXEN) ........... 309
Timer0 and Timer1 External Clock ........... 397, 429, 461
Timer1 Incrementing Edge........................................ 195
Two Speed Start-up .................................................... 77
Type-A in 1/2 Mux, 1/2 Bias Drive ............................ 343
Type-A in 1/2 Mux, 1/3 Bias Drive ............................ 345
Type-A in 1/3 Mux, 1/2 Bias Drive ............................ 347
Type-A in 1/3 Mux, 1/3 Bias Drive ............................ 349
Type-A in 1/4 Mux, 1/3 Bias Drive ............................ 351
Type-A/Type-B in Static Drive................................... 342
Type-B in 1/2 Mux, 1/2 Bias Drive ............................ 344
Type-B in 1/2 Mux, 1/3 Bias Drive ............................ 346
Type-B in 1/3 Mux, 1/2 Bias Drive ............................ 348
Type-B in 1/3 Mux, 1/3 Bias Drive ............................ 350
Type-B in 1/4 Mux, 1/3 Bias Drive ............................ 352
USART Synchronous Receive (Master/Slave)
USART Synchronous Transmission (Master/Slave
Wake-up from Interrupt ............................................. 108
PLL Clock.................................................. 393, 425, 457
I
I2C Bus Start/Stop Bits ............................. 406, 438, 470
SPI Mode .................................................. 405, 437, 469
2
2
2
2
2
2
C Bus Data ............................................. 406, 438, 470
C Bus Start/Stop Bits.............................. 405, 437, 469
C Master Mode (7 or 10-Bit Transmission) ............ 271
C Master Mode (7-Bit Reception)........................... 273
C Stop Condition Receive or Transmit Mode ......... 274
C Bus Data ............................................. 407, 439, 471
Firmware Restart .............................................. 224
)......................................................... 401, 433, 465
.......................................................... 402, 434, 466
Preliminary
TRISD ............................................................................... 140
TRISD Register........................................................... 40, 141
TRISE ............................................................................... 143
TRISE Register........................................................... 40, 144
Two-Speed Clock Start-up Mode........................................ 76
TXCON (Timer2/4/6) Register .......................................... 205
TXREG ............................................................................. 289
TXREG Register ................................................................. 42
TXSTA Register.......................................................... 42, 296
U
USART
V
V
W
Wake-up on Break ............................................................ 305
Wake-up Using Interrupts ................................................. 108
Watchdog Timer (WDT)...................................................... 86
WCOL ....................................................... 267, 270, 272, 274
WCOL Status Flag.................................... 267, 270, 272, 274
WDTCON Register ........................................................... 111
WPUB Register................................................................. 136
Write Protection .................................................................. 65
WWW Address ................................................................. 503
WWW, On-Line Support ..................................................... 11
REF
PIC16F193X/LF193X
BRGH Bit .................................................................. 299
Synchronous Master Mode
. S
Modes....................................................................... 110
Specifications ........................................... 397, 429, 461
EE
Requirements, Synchronous Receive402, 434, 466
Requirements, Synchronous Transmission
Timing Diagram, Synchronous Receive
Timing Diagram, Synchronous Transmission
ADC Reference Voltage
................................................. 402, 434, 466
................................................. 402, 434, 466
................................................. 401, 433, 465
DS41364D-page 503