DSPIC30F3012-20I/SO Microchip Technology, DSPIC30F3012-20I/SO Datasheet
DSPIC30F3012-20I/SO
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... Microchip Technology Inc. Data Sheet High-Performance, 16-bit Digital Signal Controllers DS70139F ...
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... PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... All DSP instructions are single cycle - Multiply-Accumulate (MAC) operation • single-cycle ±16 shift © 2008 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Peripheral Features: • High-current sink/source I/O pins: 25 mA/25 mA • Three 16-bit timers/counters; optionally pair up 16-bit timers into 32-bit timer modules • ...
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... Sensor Family Program Memory Device Pins Bytes Instructions dsPIC30F2011 18 12K 4K dsPIC30F3012 18 24K 8K dsPIC30F2012 28 12K 4K dsPIC30F3013 28 24K 8K DS70139F-page 4 Output SRAM EEPROM Timer Input Comp/Std Bytes Bytes 16-bit Cap PWM 1024 – 2048 1024 3 2 1024 – 2048 1024 3 2 A/D 12-bit ...
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... PDIP and SOIC EMUD3/AN0/V EMUC3/AN1/V AN2/SS1/LVDIN/CN4/RB2 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 28-Pin SPDIP and SOIC EMUD3/AN0/V EMUC3/AN1/V AN2/SS1/LVDIN/CN4/RB2 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 Note: For descriptions of individual pins, see Section 1.0 “Device Overview”. © 2008 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 MCLR +/CN2/RB0 2 17 REF AV SS -/CN3/RB1 ...
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... Pin Diagrams 28-Pin QFN AN2/SS1/LVDIN/CN4/RB2 AN3/CN5/RB3 OSC1/CLKI OSC2/CLKO/RC15 Note: For descriptions of individual pins, see Section 1.0 “Device Overview”. DS70139F-page dsPIC30F2011 PGC/EMUC/AN5/U1RX/SDI1/SDA/CN7/RB5 15 © 2008 Microchip Technology Inc. ...
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... Pin Diagrams 28-Pin QFN AN2/SS1/LVDIN/CN4/RB2 AN3/CN5/RB3 AN4/CN6/RB4 AN5/CN7/RB5 OSC1/CLKI OSC2/CLKO/RC15 Note: For descriptions of individual pins, see Section 1.0 “Device Overview”. © 2008 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 1 21 AN8/OC1/RB8 2 20 AN9/OC2/RB9 3 19 CN17/RF4 dsPIC30F2012 4 18 CN18/RF5 PGC/EMUC/U1RX/SDI1/SDA/RF2 15 DS70139F-page 7 ...
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... Pin Diagram 44-Pin QFN PGC/EMUC/AN5/U1RX/SDI1/SDA/CN7/RB5 Note: For descriptions of individual pins, see Section 1.0 “Device Overview”. DS70139F-page dsPIC30F3012 OSC2/CLKO/RC15 OSC1/CLKI AN3/CN5/RB3 NC AN2/SS1/LVDIN/CN4/RB2 © 2008 Microchip Technology Inc. ...
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... Pin Diagrams 44-Pin QFN PGC/EMUC/U1RX/SDI1/SDA/RF2 U2TX/CN18/RF5 U2RX/CN17/RF4 AN9/OC2/RB9 AN8/OC1/RB8 Note: For descriptions of individual pins, see Section 1.0 “Device Overview”. © 2008 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 dsPIC30F3013 OSC2/CLKO/RC15 OSC1/CLKI AN5/CN7/RB5 AN4/CN6/RB4 AN3/CN5/RB3 NC AN2/SS1/LVDIN/CN4/RB2 DS70139F-page 9 ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS70139F-page 10 © 2008 Microchip Technology Inc. ...
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... The following block diagrams depict the architecture for these devices: • Figure 1-1 illustrates the dsPIC30F2011 • Figure 1-2 illustrates the dsPIC30F2012 • Figure 1-3 illustrates the dsPIC30F3012 • Figure 1-4 illustrates the dsPIC30F3013 Following the block diagrams, Table 1-1 relates the I/O functions to pinout information. ...
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... Decode PORTC 16 16 DSP Divide Engine Unit ALU<16> PORTD Input Output 2 Capture Compare I C™ Module Module Timers SPI1 UART1 EMUD3/AN0/V +/CN2/RB0 REF EMUC3/AN1/V -/CN3/RB1 REF AN2/SS1/LVDIN/CN4/RB2 AN3/CN5/RB3 PGD/EMUD/AN4/U1TX/SDO1/SCL/CN6/RB4 PGC/EMUC/AN5/U1RX/SDI1/SDA/CN7/RB5 AN6/SCK1/INT0/OCFA/RB6 EMUD2/AN7/OC2/IC2/INT2/RB7 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 OSC2/CLKO/RC15 EMUC2/OC1/IC1/INT1/RD0 © 2008 Microchip Technology Inc. ...
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... Oscillator OSC1/CLKI Generation Start-up Timer POR/BOR Reset Watchdog MCLR Timer Low-Voltage Detect 12-bit ADC Capture Module © 2008 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 X Data Bus Data Latch Data Latch Y Data X Data 16 RAM RAM (512 bytes) (512 bytes) 16 Address Address Latch Latch 16 16 ...
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... FIGURE 1-3: dsPIC30F3012 BLOCK DIAGRAM Y Data Bus Interrupt PSV & Table Controller Data Access 8 24 Control Block 24 24 PCH PCU Program Counter Stack Address Latch Control Logic Program Memory (24 Kbytes) Data EEPROM (1 Kbytes) 16 Data Latch ROM Latch 24 16 Instruction Decode & ...
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... Timer Timing Oscillator OSC1/CLKI Generation Start-up Timer POR/BOR Reset Watchdog MCLR Timer Low-Voltage Detect 12-bit ADC Capture Module © 2008 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 X Data Bus Data Latch Data Latch X Data Y Data 16 RAM RAM (1 Kbytes) (1 Kbytes) 16 Address Address Latch Latch RAGU ...
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... PORTC is a bidirectional I/O port. ST PORTD is a bidirectional I/O port. ST PORTF is a bidirectional I/O port. ST Synchronous serial clock input/output for SPI1. ST SPI1 Data In. — SPI1 Data Out. ST SPI1 Slave Synchronization. Analog = Analog input O = Output P = Power Description © 2008 Microchip Technology Inc. ...
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... I REF Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input © 2008 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Buffer Type ST Synchronous serial clock input/output for I ST Synchronous serial data input/output for I — 32 kHz low-power oscillator crystal output. ST/CMOS 32 kHz low-power oscillator crystal input. ST buffer when configured in RC mode ...
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... NOTES: DS70139F-page 18 © 2008 Microchip Technology Inc. ...
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... Each data word consists of 2 bytes and most instructions can address data either as words or bytes. © 2008 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Two ways to access data in program memory are: • The upper 32 Kbytes of data space memory can ...
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... The upper byte of the STATUS register contains the DSP Adder/Subtracter Status bits, the DO Loop Active bit (DA) and the Digit Carry (DC) Status bit. 2.2.3 PROGRAM COUNTER The program counter is 23 bits wide; bit 0 is always clear. Therefore, the PC can address instruction words. © 2008 Microchip Technology Inc. ...
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... AD39 DSP ACCA Accumulators ACCB PC22 0 7 TABPAG TBLPAG Data Table Page Address 7 0 PSVPAG PSVPAG OAB SAB DA SRH © 2008 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 D15 D0 W0/WREG W10 W11 W12/DSP Offset W13/DSP Write-Back W14/Frame Pointer W15/Stack Pointer SPLIM AD15 AD31 PC0 ...
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... The REPEAT loop count must be setup for 18 iterations of the DIV/DIVF instruction. Thus, a complete divide operation requires 19 cycles. Note: The divide flow is interruptible. However, the user needs to save the context as appropriate. Function © 2008 Microchip Technology Inc. of execution ...
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... ED EDAC MAC MAC MOVSAC MPY MPY.N MSC © 2008 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 The DSP engine has various options selected through various bits in the CPU Core Configuration register (CORCON), as listed below: 1. Fractional or integer DSP multiply (IF). 2. Signed or unsigned DSP multiply (US). ...
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... FIGURE 2-2: DSP ENGINE BLOCK DIAGRAM 40 Carry/Borrow Out Carry/Borrow In DS70139F-page 24 40-bit Accumulator A 40-bit Accumulator B Saturate Adder Negate Barrel 16 Shifter 40 Sign-Extend 17-bit Multiplier/Scaler 16 16 To/From W Array Round u Logic Zero Backfill © 2008 Microchip Technology Inc. ...
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... For the ADD and LAC instructions, the data to be accumulated or loaded can be optionally scaled via the barrel shifter prior to accumulation. © 2008 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 2.4.2.1 The adder/subtracter is a 40-bit adder with an optional zero input into one side and either true or complement data into the other input ...
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... Section 2.4.2.4 “Data Space Write Saturation”). Note that for the MAC class of instructions, the accumulator write-back operation functions in the same manner, addressing combined MCU (X and Y) data space though the X bus. For this class of instructions, the data is always subject to rounding. © 2008 Microchip Technology Inc. saturation, see ...
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... If the SATDW bit in the CORCON register is not set, the input data is always passed through unmodified under all conditions. © 2008 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 2.4.3 BARREL SHIFTER The barrel shifter is capable of performing up to 16-bit arithmetic or logic right shifts 16-bit left shifts in a single cycle ...
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... NOTES: DS70139F-page 28 © 2008 Microchip Technology Inc. ...
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... Figure 3-1. The pro- gram space memory map for the dsPI30F3012/3013 is shown in Figure 3-2. © 2008 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Program memory is addressable by a 24-bit value from either the 23-bit PC, table instruction Effective Address (EA), or data space EA, when program space is mapped into data space as defined by Table 3-1 ...
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... F7FFFE F80000 F8000E F80010 FEFFFE FF0000 FFFFFE dsPIC30F3012/3013 PROGRAM SPACE MEMORY MAP Reset - GOTO Instruction 000000 Reset - Target Address 000002 000004 Interrupt Vector Table Vector Tables 00007E Reserved 000080 Alternate Vector Table 000084 ...
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... Program 0 Space Visibility Using 1/0 Table Instruction User/ Configuration Space Select Note: Program space visibility cannot be used to access bits <23:16> word in program memory. © 2008 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Program Space Address <23> <22:16> 0 TBLPAG<7:0> TBLPAG<7:0> PSVPAG<7:0> bits Program Counter Select 1 ...
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... P<23:16> maps to the destination byte when byte select = 0; The destination byte will always when byte select = 1. 4. TBLWTH: Table Write High (refer to Section 5.0 “Flash Program Memory” for details on Flash Programming TBLRDL.W TBLRDL.B (Wn<0> TBLRDL.B (Wn<0> © 2008 Microchip Technology Inc. ...
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... The upper 8 bits should be programmed to force an illegal instruction to maintain machine robustness. Refer to the “dsPIC30F/33F Programmer’s Reference Manual” (DS70157) for details on instruction encoding. © 2008 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 TBLRDH TBLRDH.B (Wn<0> TBLRDH.B (Wn< ...
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... W0 ; Access program memory location ; using a data space access Note 1: PSVPAG is an 8-bit register, containing bits <22:15> of the program space address. DS70139F-page 34 Program Space 0x0000 (1) PSVPAG 0x00 8 0x8000 23 15 Address Concatenation 15 23 0xFFFF 0x000000 0 0x001200 0x001FFF Data Read © 2008 Microchip Technology Inc. ...
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... W8 and W9. Both address spaces are concurrently accessed only with the MAC class instructions. The data space memory map for the dsPIC30F2011 and dsPIC30F2012 is shown in Figure 3-7. The data space memory map for the dsPIC30F3012 and dsPIC30F3013 is shown in Figure 3-8. 16 bits MSB LSB ...
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... FIGURE 3-8: dsPIC30F3012/3013 DATA SPACE MEMORY MAP MSB Address 0x0001 2 Kbyte SFR Space 0x07FF 0x0801 0x0BFF 2 Kbyte 0x0C01 SRAM Space 0x0FFF 0x1001 0x1FFF 0x8001 Optionally Mapped into Program Memory 0xFFFF DS70139F-page 36 LSB 16 bits Address MSB LSB 0x0000 SFR Space 0x07FE ...
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... FIGURE 3-9: DATA SPACE FOR MCU AND DSP (MAC CLASS) INSTRUCTIONS EXAMPLE SFR SPACE (Y SPACE) Non-MAC Class Ops (Read/Write) MAC Class Ops (Write) Indirect EA using any W © 2008 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 UNUSED Y SPACE UNUSED MAC Class Ops (Read) Indirect EA using W8, W9 ...
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... FIGURE 3-10: MSB 15 0001 Byte 1 Byte 3 0003 0x0000 Byte 5 0x0000 0005 0x0000 backward compatibility with DATA ALIGNMENT LSB 0000 Byte 0 Byte 2 0002 Byte 4 0004 © 2008 Microchip Technology Inc. ...
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... PC<22:16> 000000000 <Free Word> W15 (after CALL) POP : [--W15] PUSH : [W15++] © 2008 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 There is a Stack Pointer Limit register (SPLIM) associated with uninitialized at Reset the case for the Stack Pointer, SPLIM<0> is forced to ‘0’ because all stack operations must be word aligned ...
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TABLE 3-3: CORE REGISTER MAP Address SFR Name Bit 15 Bit 14 Bit 13 Bit 12 (Home) W0 0000 W1 0002 W2 0004 W3 0006 W4 0008 W5 000A W6 000C W7 000E W8 0010 W9 0012 W10 0014 W11 ...
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TABLE 3-3: CORE REGISTER MAP (CONTINUED) Address SFR Name Bit 15 Bit 14 Bit 13 Bit 12 (Home) CORCON 0044 — — — US MODCON 0046 XMODEN YMODEN — XMODSRT 0048 XMODEND 004A YMODSRT 004C YMODEND 004E XBREV 0050 BREN ...
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... NOTES: DS70139F-page 42 © 2008 Microchip Technology Inc. ...
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... Register Indirect Register Indirect Post-modified Register Indirect Pre-modified Register Indirect with Register Offset The sum of Wn and Wb forms the EA. Register Indirect with Literal Offset © 2008 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 4.1.1 FILE REGISTER INSTRUCTIONS Most file register instructions use a 13-bit address field (f) to directly address data present in the first 8192 bytes of data memory (near data space) ...
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... As these buffers satisfy the Start and the end address criteria, they can operate in a Bidirectional mode (i.e., address boundary checks are performed on both the lower and upper address boundaries). buffers), or end address © 2008 Microchip Technology Inc. ...
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... MODULO ADDRESSING OPERATION EXAMPLE Byte Address 0x1100 0x1163 Start Addr = 0x1100 End Addr = 0x1163 Length = 0x0032 words © 2008 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 4.2.2 W ADDRESS REGISTER SELECTION The Modulo and Bit-Reversed Addressing Control registers: register, MODCON<15:0>, contains enable flags as well register field to specify the W address registers ...
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... If Bit-Reversed Addressing has already been enabled by setting the BREN (XBREV<15>) bit, then a write to the XBREV register should not be immediately followed by an indirect read operation using the W register that has been designated as the bit-reversed pointer. N bytes, should not be enabled Bit-Reversed Addressing © 2008 Microchip Technology Inc. ...
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... TABLE 4-3: BIT-REVERSED ADDRESS MODIFIER VALUES FOR XBREV REGISTER Buffer Size (Words) 1024 512 256 128 © 2008 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Sequential Address Bit-Reversed Address Pivot Point XB = 0x0008 for a 16-word Bit-Reversed Buffer Bit-Reversed Address Decimal XB<14:0> Bit-Reversed Address Modifier Value ...
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... NOTES: DS70139F-page 48 © 2008 Microchip Technology Inc. ...
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... Using NVMADR Addressing Using Table Instruction User/Configuration Space Select © 2008 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 5.2 Run-Time Self-Programming (RTSP) RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions. With RTSP, the user may erase program memory, 32 instructions (96 bytes time and can write program memory data, 32 instructions (96 bytes time ...
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... NVMKEY register. Refer to Section 5.6 “Programming Operations” for further details. DD Note: The user can also directly write to the NVMADR and NVMADRU registers to specify a program memory address for erasing or programming. © 2008 Microchip Technology Inc. ...
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... MOV #0xAA,W1 MOV W1 NVMKEY , BSET NVMCON,#WR NOP NOP © 2008 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 4. Write 32 instruction words of data from data RAM “image” into the program Flash write latches. 5. Program 32 instruction words into program Flash. a) Set up NVMCON register for multi-word, the ...
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... Write PM low word into program latch ; Write PM high byte into program latch ; Block all interrupts with priority <7 for ; next 5 instructions ; ; Write the 0x55 key ; ; Write the 0xAA key ; Start the erase sequence ; Insert two NOPs after the erase ; command is asserted © 2008 Microchip Technology Inc. ...
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TABLE 5-1: NVM REGISTER MAP File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 NVMCON 0760 WR WREN WRERR NVMADR 0762 NVMADRU 0764 — — — NVMKEY 0766 — — — Legend: ...
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... NOTES: DS70139F-page 54 © 2008 Microchip Technology Inc. ...
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... A word write operation should be preceded by an erase of the corresponding memory location(s). The write typically requires complete, but the write time varies with voltage and temperature. © 2008 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 A program or erase operation on the data EEPROM does not stop the instruction flow. The user is ...
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... Block all interrupts with priority <7 for ; next 5 instructions ; ; Write the 0x55 key ; ; Write the 0xAA key ; Initiate erase sequence ; Block all interrupts with priority <7 for ; next 5 instructions ; ; Write the 0x55 key ; ; Write the 0xAA key ; Initiate erase sequence © 2008 Microchip Technology Inc. ...
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... NOP ; Write cycle will complete in 2mS. CPU is not stalled for the Data Write Cycle ; User can poll WR bit, use NVMIF or Timer IRQ to determine write complete © 2008 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 The write does not initiate if the above sequence is not exactly followed (write 0x55 to NVMKEY, write 0xAA to NVMCON, then set WR bit) for each word ...
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... EEPROM writes, various mechanisms have been built-in. On power-up, the WREN bit is cleared; also, the Power-up Timer prevents EEPROM write. The write initiate sequence and the WREN bit together help prevent an accidental write during brown-out, power glitch, or software malfunction. © 2008 Microchip Technology Inc. ...
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... WR TRIS WR LAT + WR Port Read LAT Read Port © 2008 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Writes to the latch, write the latch (LATx). Reads from the port (PORTx), read the port pins and writes to the port pins, write the latch (LATx). Any bit and its associated data and Control registers that are not valid for a particular device are disabled ...
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... Typically this instruction have their would be a NOP EXAMPLE 7-1: MOV #0xF0, W0; Configure PORTB<7:4> MOV W0, TRISB; and PORTB<3:0> as outputs NOP btss PORTB, #7; bit test RB7 and skip if set PORT WRITE/READ EXAMPLE ; as inputs ; additional instruction cycle © 2008 Microchip Technology Inc. ...
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TABLE 7-1: PORTB REGISTER MAP FOR dsPIC30F2011/3012 SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name TRISB 02C6 — — — — PORTB 02C8 — — — — LATB 02CB — — — — Legend: — = unimplemented ...
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TABLE 7-5: PORTD REGISTER MAP FOR dsPIC30F2012/3013 SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name TRISD 02D2 — — — — PORTD 02D4 — — — — LATD 02D6 — — — — Legend: — = unimplemented ...
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... CN7PUE CN6PUE CNPU2 00C6 — — Legend: — = unimplemented bit, read as ‘0’ Note: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. © 2008 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Bit 5 Bit 4 Bit 3 Bit 2 CN5IE CN4IE CN3IE CN2IE — ...
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... NOTES: DS70139F-page 64 © 2008 Microchip Technology Inc. ...
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... The current CPU priority level is explicitly stored in the IPL bits. IPL<3> is present in the CORCON register, whereas IPL<2:0> are present in the STATUS register (SR) in the processor core. © 2008 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 • INTCON1<15:0>, INTCON2<15:0> Global interrupt control functions are derived from these two registers ...
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... U2TX* — UART2 Transmitter 26-41 34-49 Reserved 42 50 LVD — Low-Voltage Detect 43-53 51-61 Reserved Lowest Natural Order Priority * Only the dsPIC30F3013 has UART2 and the U2RX, U2TX interrupts. These locations are reserved for the dsPIC30F2011/2012/3012. © 2008 Microchip Technology Inc. ...
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... A momentary dip in the power supply to the device has been detected which may result in malfunction. • Trap Lockout: Occurrence of multiple trap conditions simultaneously causes a Reset. © 2008 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 8.3 Traps Traps can be considered as non-maskable interrupts indicating a software or hardware error, which adhere to a predefined priority as shown in Figure 8-1 ...
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... The device is automatically Reset in a hard trap conflict condition. The TRAPR Status bit (RCON<15>) is set when the Reset occurs, so that the condition may be detected in software. © 2008 Microchip Technology Inc. ...
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... The processor then loads the priority level for this internsrupt into the STATUS register. This action disables all lower priority interrupts until the completion of the Interrupt Service Routine. © 2008 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 FIGURE 8-2: 0x000000 0x000002 ...
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... If an enabled interrupt request of sufficient priority is received by the interrupt controller, then the standard interrupt request is presented to the processor. At the same time, the processor wakes up from Sleep or Idle and begins execution of the Interrupt Service Routine (ISR) needed to process the interrupt request. © 2008 Microchip Technology Inc. ...
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TABLE 8-2: dsPIC30F2011/2012/3012 INTERRUPT CONTROLLER REGISTER MAP SFR ADR Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Name INTCON1 0080 NSTDIS — — — — INTCON2 0082 ALTIVT DISI — — — IFS0 0084 CNIF MI2CIF SI2CIF NVMIF ...
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TABLE 8-3: dsPIC30F3013 INTERRUPT CONTROLLER REGISTER MAP SFR ADR Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Name INTCON1 0080 NSTDIS — — — — INTCON2 0082 ALTIVT DISI — — — IFS0 0084 CNIF MI2CIF SI2CIF NVMIF ...
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... TGATE SOSCO/ T1CK LPOSCEN SOSCI © 2008 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 These operating modes are determined by setting the appropriate bit(s) in the 16-bit SFR, T1CON. Figure 9-1 presents a block diagram of the 16-bit timer module. 16-bit Timer Mode: In the 16-bit Timer mode, the timer ...
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... Low power • Real-Time Clock interrupts These operating modes are determined by setting the appropriate bit(s) in the T1CON Control register. FIGURE 9-2: RECOMMENDED COMPONENTS FOR TIMER1 LP OSCILLATOR RTC C1 32.768 kHz XTAL pF 100K © 2008 Microchip Technology Inc. SOSCI dsPIC30FXXXX SOSCO ...
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... The TSIDL bit should be cleared to ‘0’ in order for RTC to continue operation in Idle mode. © 2008 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 9.5.2 RTC INTERRUPTS When an interrupt event occurs, the respective interrupt flag, T1IF, is asserted and an interrupt is generated if enabled ...
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TABLE 9-1: TIMER1 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 TMR1 0100 PR1 0102 T1CON 0104 TON — TSIDL — Legend uninitialized bit; — = unimplemented bit, read as ‘0’ Note: Refer ...
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... Interrupt on a 32-bit period register match These operating modes are determined by setting the appropriate bit(s) in the 16-bit T2CON and T3CON SFRs. © 2008 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 For 32-bit timer/counter operation, Timer2 is the ls word and Timer3 is the ms word of the 32-bit timer. ...
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... Timer Configuration bit T32 (T2CON<3>) must be set to ‘ bits are respective to the T2CON register. DS70139F-page TMR3 TMR2 MSB LSB Comparator x 32 PR3 PR2 TGATE (T2CON<6> Gate Sync ’ for a 32-bit timer/counter operation. All control Sync TCKPS<1:0> TON 2 Prescaler 1, 8, 64, 256 © 2008 Microchip Technology Inc. ...
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... TIMER2 BLOCK DIAGRAM Equal Reset 0 T2IF Event Flag 1 TGATE T2CK FIGURE 10-3: 16-BIT TIMER3 BLOCK DIAGRAM ADC Event Trigger Equal Reset 0 T3IF Event Flag 1 TGATE T3CK © 2008 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 PR2 Comparator x 16 TMR2 TGATE Gate Sync PR3 Comparator x 16 TMR3 ...
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... T3IF bit (IFS0<7>) is asserted and an interrupt is generated if enabled. In this mode, the T3IF interrupt flag is used as the source of the interrupt. The T3IF bit must be cleared in software. Enabling an interrupt is accomplished via the respective timer interrupt enable bit, T3IE (IEC0<7>). © 2008 Microchip Technology Inc. can generate an ...
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TABLE 10-1: TIMER2/3 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 TMR2 0106 TMR3HLD 0108 TMR3 010A PR2 010C PR3 010E T2CON 0110 TON — TSIDL — T3CON 0112 TON — TSIDL — ...
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... NOTES: DS70139F-page 82 © 2008 Microchip Technology Inc. ...
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... Data Bus Note: Where ‘x’ is shown, reference is made to the registers or bits associated to the respective input capture channel (1 or 2). © 2008 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 • Interrupt on input capture event These operating modes are determined by setting the appropriate bits in the IC1CON and IC2CON registers. ...
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... Each channel provides an interrupt flag (ICxIF) bit. The respective capture channel interrupt flag is located in the corresponding IFSx register. Enabling an interrupt is accomplished via the respective capture channel interrupt enable (ICxIE) bit. The capture interrupt enable bit is located in the corresponding IEC Control register. © 2008 Microchip Technology Inc. satisfied. defined as ...
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TABLE 11-1: INPUT CAPTURE REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 IC1BUF 0140 IC1CON 0142 — — ICSIDL — IC2BUF 0144 IC2CON 0146 — — ICSIDL — Legend uninitialized bit; — = ...
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... NOTES: DS70139F-page 86 © 2008 Microchip Technology Inc. ...
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... TMR2<15:0 TMR3<15:0> Note: Where ‘x’ is shown, reference is made to the registers associated with the respective output compare channel (1 or 2). © 2008 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Figure 12-1 depicts a block diagram of the output compare module. The key operational features of the output compare module include: • ...
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... Fault condition has occurred. This state is maintained until both of the following events have occurred: • The external Fault condition has been removed. • The PWM mode has been re-enabled by writing to the appropriate control bits © 2008 Microchip Technology Inc. ...
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... Timer3) is enabled and the TSIDL bit of the selected timer is set to logic ‘0’. © 2008 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 When the selected TMRx is equal to its respective period register, PRx, the following four events occur on the next increment cycle: • ...
Page 90
TABLE 12-1: OUTPUT COMPARE REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 OC1RS 0180 OC1R 0182 OC1CON 0184 — — OCSIDL — OC2RS 0186 OC2R 0188 OC2CON 018A — — OCSIDL — Legend: ...
Page 91
... The module will not respond to SCL transitions while SPIROV is ‘1’, effec- tively disabling the module until SPI1BUF is read by user software. © 2008 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Transmit writes are also double-buffered. The user writes to SPI1BUF. When the master or slave transfer is completed, the contents of the shift register (SPI1SR) are moved to the receive buffer ...
Page 92
... Synchronization Pulse). The frame pulse is an active-high pulse for a single SPI clock cycle. When Frame Synchronization transmission starts only on the subsequent transmit edge of the SPI clock. Secondary Primary F Prescaler CY Prescaler 1:1 – generates the Frame is enabled, the data © 2008 Microchip Technology Inc. ...
Page 93
... CPU enters Sleep mode while an SPI transaction is in progress, then the transmission and reception is aborted. The transmitter and receiver will stop in Sleep mode. However, register contents are not affected by entering or exiting Sleep mode. © 2008 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 SDO1 SDI1 SDI1 SDO1 ...
Page 94
TABLE 13-1: SPI1 REGISTER MAP SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Name SPI1STAT 0220 SPIEN — SPISIDL — SPI1CON 0222 — FRMEN SPIFSD — DISSDO MODE16 SPI1BUF 0224 Legend: — = unimplemented bit, read ...
Page 95
... Thus, the I C module can operate either as a slave master bus. FIGURE 14-1: PROGRAMMER’S MODEL Bit 15 Bit 15 © 2008 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 14.1.1 VARIOUS I The following types • slave operation with 7-bit address 2 • slave operation with 10-bit address 2 • ...
Page 96
... LSB Addr_Match I2CADD Start and Start, Restart, Collision Detect Acknowledge Generation Clock Stretching I2CTRN LSB Reload Control I2CBRG BRG Down Counter F CY Internal Data Bus Read Write Read Write Read Write Read Write Read Write Read © 2008 Microchip Technology Inc. ...
Page 97
... SDA is valid during SCL high. The interrupt pulse is sent on the falling edge of the ninth clock pulse, regardless of the status of the ACK received from the master. © 2008 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 14.3.2 SLAVE RECEPTION If the R_W bit received is a ‘0’ during an address match, then Receive mode is initiated ...
Page 98
... C bus have de-asserted SCL. This ensures that a write to the SCLREL bit will not violate the minimum high time requirement for SCL. If the STREN bit is ‘0’, a software write to the SCLREL bit will be disregarded and have no effect on the SCLREL bit. © 2008 Microchip Technology Inc. ...
Page 99
... When the interrupt is serviced, the source for the interrupt can be checked by reading the contents of the I2CRCV to determine if the address was device specific or a general call address. © 2008 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 2 14. Master Support ...
Page 100
... Idle or continue on Idle. If I2CSIDL = 0, the module will continue operation on assertion of the Idle mode. If I2CSIDL = 1, the module will stop on Idle master event Interrupt Service 2 C bus is free (i.e., the P bit is set), the C bus is free, the user can resume 2 © 2008 Microchip Technology Inc. C ...
Page 101
TABLE 14- REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 I2CRCV 0200 — — — — I2CTRN 0202 — — — — I2CBRG 0204 — — — — I2CCON 0206 I2CEN — ...
Page 102
... NOTES: DS70139F-page 102 © 2008 Microchip Technology Inc. ...
Page 103
... Internal Data Bus UTXBRK Data UxTX Parity Note © 2008 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 15.1 UART Module Overview The key features of the UART module are: • Full-duplex 9-bit data communication • Even, odd or no parity options (for 8-bit data) • One or two Stop bits • ...
Page 104
... Receive Buffer Control 8-9 Load RSR to Buffer Receive Shift Register (UxRSR) 16 Divider 16x Baud Clock from Baud Rate Generator Read Read Write UxMODE UxSTA – Generate Flags – Generate Interrupt – Shift Data Characters Control Signals UxRXIF © 2008 Microchip Technology Inc. ...
Page 105
... The STSEL bit determines whether one or two Stop bits will be used during data transmission. The default (power-on) setting of the UART is 8 bits, no parity and 1 Stop bit (typically represented 1). © 2008 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 15.3 Transmitting Data 15.3.1 ...
Page 106
... UxRSR needs to transfer the character to the buffer. Once OERR is set, no further data is shifted in UxRSR (until the OERR bit is cleared in software or a Reset occurs). The data held in UxRSR and UxRXREG remains valid. RXB) X the settings specified by © 2008 Microchip Technology Inc. ...
Page 107
... FERR bit set. The Break character is loaded into the buffer. No further reception can occur until a Stop bit is received. Note that RIDLE goes high when the Stop bit has not yet been received. © 2008 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 15.6 Address Detect Mode Setting the ADDEN bit (UxSTA< ...
Page 108
... For the UART, the USIDL bit selects if the module will stop operation when the device enters Idle mode or whether the module will continue on Idle. If USIDL = 0, the module will continue to operate during Idle mode. If USIDL = 1, the module will stop on Idle. © 2008 Microchip Technology Inc. ...
Page 109
TABLE 15-1: UART1 REGISTER MAP FOR dsPIC30F2011/2012/3012/3013 SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 U1MODE 020C UARTEN — USIDL — U1STA 020E UTXISEL — — — UTXBRK UTXEN U1TXREG 0210 — — — — ...
Page 110
... NOTES: DS70139F-page 110 © 2008 Microchip Technology Inc. ...
Page 111
... AN6 0111 AN7 1000 AN8 1001 AN9 © 2008 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 on the (V REF feature of being able to operate while the device is in Sleep mode with RC oscillator selection. The ADC module has six 16-bit registers: • A/D Control Register 1 (ADCON1) • ...
Page 112
... The inputs are always scanned from lower to higher numbered inputs, starting after each interrupt. If the number of inputs selected is greater than the number of samples taken per interrupt, the higher numbered inputs are unused. © 2008 Microchip Technology Inc. number of ...
Page 113
... There are 64 possible options for T EQUATION 16-1: ADC CONVERSION CLOCK (0.5*(ADCS<5:0> © 2008 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 The internal RC oscillator is selected by setting the ADRC bit. For correct ADC conversions, the ADC conversion clock (T ) must be selected to ensure a minimum T AD time of 334 nsec (for V “ ...
Page 114
... dsPIC30F2011 Channels Configuration REF REF CH X ANx S/H ADC REF REF ANx S/H ADC ANx REF See Note μF 0.1 μF 0.01 μ μF 0.1 μF 0.01 μF pin. DD © 2008 Microchip Technology Inc. ...
Page 115
... DAC) HOLD Note: C value depends on device package and is not tested. Effect of C PIN © 2008 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 The following figure shows the timing diagram of the ADC running at 200 ksps. The T conjunction with the guidelines described above allows a conversion speed of 200 ksps ...
Page 116
... Each of the output formats translates to a 16-bit result on the data bus. d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 © 2008 Microchip Technology Inc. ...
Page 117
... Analog levels on any pin that is defined as a digital input (including the ANx pins) may cause the input buffer to consume current that exceeds the device specifications. © 2008 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 16.14 Connection Considerations The analog inputs have diodes to V protection ...
Page 118
TABLE 16-2: A/D CONVERTER REGISTER MAP FOR dsPIC30F2011/3012 SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name ADCBUF0 0280 — — — — ADCBUF1 0282 — — — — ADCBUF2 0284 — — — — ADCBUF3 0286 — ...
Page 119
TABLE 16-3: A/D CONVERTER REGISTER MAP FOR dsPIC30F2012/3013 SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name ADCBUF0 0280 — — — — ADCBUF1 0282 — — — — ADCBUF2 0284 — — — — ADCBUF3 0286 — ...
Page 120
... NOTES: DS70139F-page 120 © 2008 Microchip Technology Inc. ...
Page 121
... In the Idle mode, the clock sources are still active but the CPU is shut-off. The RC oscillator option saves system cost while the LP crystal option saves power. © 2008 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 17.1 Oscillator System Overview The dsPIC30F oscillator system has the following modules and features: • ...
Page 122
... RC oscillator. Note 1: dsPIC30F maximum operating frequency of 120 MHz must be met oscillator can be conveniently shared as system clock, as well as real-time clock for Timer1. 3: Requires external R and C. Frequency operation MHz. DS70139F-page 122 Description (1) . (2) . (1) . (1) . (1) . (3) /4 output . OSC (3) . © 2008 Microchip Technology Inc. ...
Page 123
... FIGURE 17-1: OSCILLATOR SYSTEM BLOCK DIAGRAM OSC1 Primary Oscillator OSC2 Internal Fast RC Oscillator (FRC) POR Done SOSCO 32 kHz LP Oscillator SOSCI © 2008 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 F PLL PLL x4, x8, x16 PLL Lock Primary Osc Internal FRC Osc Primary Oscillator Stability Detector ...
Page 124
... OSC2 Function OSC2 0 1 OSC2 1 0 OSC2 1 1 OSC2 0 1 OSC2 1 0 OSC2 1 1 OSC2 0 1 OSC2 1 0 OSC2 OSC2 0 0 OSC2 1 0 CLKO 1 1 CLKO OSC2 0 0 (Note (Note (Note © 2008 Microchip Technology Inc. ...
Page 125
... Table 17-4. If OSCCON<14:12> are set to ‘111’ and FPR<4:0> are set to ‘00001’, ‘01010’ or ‘00011’, then a PLL multiplier (respectively) is applied. © 2008 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Note: When a 16x PLL is used, the FRC fre- quency must not be tuned to a frequency greater than 7 ...
Page 126
... To write to the OSCCON high byte, the following instructions must be executed without any other instructions in between: Byte Write “0x78” to OSCCON high Byte Write “0x9A” to OSCCON high Byte write is allowed for one instruction cycle. Write the desired value or use bit manipulation instruction. © 2008 Microchip Technology Inc. ...
Page 127
... POR timer and place the device in the Reset state. The POR also selects the device clock source identified by the oscillator configuration fuses. © 2008 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Different registers are affected in different ways by various Reset conditions. Most registers are not affected by a WDT wake-up since this is viewed as the resumption of normal operation ...
Page 128
... INTERNAL POR OST TIME-OUT PWRT TIME-OUT INTERNAL Reset FIGURE 17-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR OST TIME-OUT PWRT TIME-OUT INTERNAL Reset DS70139F-page 128 T OST T PWRT T OST T PWRT T OST T PWRT ) DD ): CASE CASE 2 DD © 2008 Microchip Technology Inc. ...
Page 129
... The BOR will select the clock source based on the device Configuration bit values (FOS<2:0> and FPR<4:0>). Furthermore Oscillator mode is © 2008 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 selected, the BOR will activate the Oscillator Start-up Timer (OST). The system clock is held until OST expires. If the PLL is used, then the clock will be held until the LOCK bit (OSCCON< ...
Page 130
... Note 1: When the wake-up is due to an enabled interrupt, the PC is loaded with the corresponding interrupt vector. DS70139F-page 130 TRAPR IOPUWR EXTR SWR WDTO IDLE SLEEP POR BOR ( TRAPR IOPUWR EXTR SWR WDTO IDLE SLEEP POR BOR ( © 2008 Microchip Technology Inc. ...
Page 131
... In some devices, the LVD threshold voltage may be applied externally on the LVDIN pin. The LVD module is enabled by setting the LVDEN bit (RCON<12>). © 2008 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 17.6 Power-Saving Modes There are two power-saving states that can be entered through the execution of a special instruction, PWRSAV; ...
Page 132
... For additional information, please refer to the Programming Specifications of the device. Note: If the code protection Configuration fuse bits (FGS<GCP> and FGS<GWRP>) have been programmed, an erase of the entire code-protected device is only possible at voltages V of the Configuration bits is ≥ 4.5V. DD © 2008 Microchip Technology Inc. ...
Page 133
... Control registers are already configured to enable module operation). Note: In the dsPIC30F2011, dsPIC30F3012 and dsPIC30F2012 devices, the U2MD bit is readable and writable and will be read as ‘1’ when set. © 2008 Microchip Technology Inc. ...
Page 134
TABLE 17-7: SYSTEM INTEGRATION REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 RCON 0740 TRAPR IOPUWR BGST LVDEN OSCCON 0742 — COSC<2:0> OSCTUN 0744 — — — — PMD1 0770 — — T3MD ...
Page 135
... The file register specified by the value ‘f’ • The destination, which could either be the file register ‘f’ or the W0 register, which is denoted as ‘WREG’ © 2008 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Most bit-oriented rotate/shift instructions) have two operands: • ...
Page 136
... Moreover, double-word moves require two cycles. The double-word instructions execute in two instruction cycles. Note: For more details on the instruction set, refer to the Programmer’s Reference Manual. indirect writes, and Description © 2008 Microchip Technology Inc. ...
Page 137
... Y data space prefetch address register for DSP instructions ∈ {[W10]+=6, [W10]+=4, [W10]+=2, [W10], [W10]-=6, [W10]-=4, [W10]-=2, [W11]+=6, [W11]+=4, [W11]+=2, [W11], [W11]-=6, [W11]-=4, [W11]-=2, [W11+W12], none} Y data space prefetch destination register for DSP instructions ∈ {W4..W7} Wyd © 2008 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Description DS70139F-page 137 ...
Page 138
... Branch if Accumulator A overflow Branch if Accumulator B overflow Branch if Overflow Branch if Accumulator A saturated Branch if Accumulator B saturated Branch Unconditionally Branch if Zero Computed Branch Bit Set f Bit Set Ws Write C bit to Ws<Wb> Write Z bit to Ws<Wb> © 2008 Microchip Technology Inc Status Flags Cycle Affected OA,OB,SA, C,DC,N,OV,Z ...
Page 139
... DEC2 DEC2 f DEC2 f,WREG DEC2 Ws,Wd 28 DISI DISI #lit14 © 2008 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Description Bit Toggle f Bit Toggle Ws Bit Test f, Skip if Clear Bit Test Ws, Skip if Clear Bit Test f, Skip if Set Bit Test Ws, Skip if Set Bit Test f Bit Test Bit Test Bit Test Ws< ...
Page 140
... Move f to WREG Move 16-bit literal to Wn Move 8-bit literal to Wn Move Move Move WREG to f Move Double from W(ns):W(ns+ Move Double from Ws to W(nd+1):W(nd) Prefetch and store accumulator © 2008 Microchip Technology Inc Status Flags Cycle Affected N,Z,C,OV ...
Page 141
... RLNC Ws,Wd 65 RRC RRC f RRC f,WREG RRC Ws,Wd © 2008 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Description Multiply Accumulator Square Wm to Accumulator -(Multiply Wm by Wn) to Accumulator Multiply and Subtract from Accumulator {Wnd+1, Wnd} = signed(Wb) * signed(Ws) {Wnd+1, Wnd} = signed(Wb) * unsigned(Ws) {Wnd+1, Wnd} = unsigned(Wb) * ...
Page 142
... Wd = lit5 - nibble swap byte swap Wn Read Prog<23:16> to Wd<7:0> Read Prog<15:0> Write Ws<7:0> to Prog<23:16> Write Ws to Prog<15:0> Unlink frame pointer .XOR. WREG WREG = f .XOR. WREG Wd = lit10 .XOR .XOR .XOR. lit5 Wnd = Zero-extend Ws © 2008 Microchip Technology Inc Status Flags Cycle Affected N N N,Z ...
Page 143
... PICSTART Plus Development Programmer - MPLAB PM3 Device Programmer - PICkit™ 2 Development Programmer • Low-Cost Demonstration and Development Boards and Evaluation Kits © 2008 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 19.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit microcontroller market ...
Page 144
... MPLAB C30 C Compilers, and the MPASM and MPLAB ASM30 Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool PC-hosted environment by ® DSCs on an © 2008 Microchip Technology Inc. ...
Page 145
... MPLAB REAL ICE offers significant advantages over competitive emulators including low-cost, full-speed emulation, real-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables. © 2008 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 19.9 MPLAB ICD 2 In-Circuit Debugger Microchip’s In-Circuit Debugger, MPLAB ICD ...
Page 146
... ICs, CAN, IrDA EE OQ ® battery management, SEEVAL evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits. © 2008 Microchip Technology Inc. kits and ® , PowerSmart ...
Page 147
... DD 4.5-5.5V -40°C to 85°C 4.5-5.5V -40°C to 125°C 3.0-3.6V -40°C to 85°C 3.0-3.6V -40°C to 125°C 2.5-3.0V -40°C to 85°C © 2008 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 (except V and MCLR) (Note 1) ..................................... -0. .......................................................................................................... ± > ................................................................................................... ± pin, inducing currents greater than 80 mA, may cause latch-up. ...
Page 148
... Notes 44 — °C — °C — °C — °C — °C/W 1 -40°C ≤ T ≤ +85°C for Industrial A -40°C ≤ T ≤ +125°C for Extended A Units Conditions V Industrial temperature V Extended temperature V/ms 0-5V in 0.1 sec 0- © 2008 Microchip Technology Inc. ...
Page 149
... All I/O pins are configured as Inputs and pulled to V MCLR = V , WDT, FSCM, LVD and BOR are disabled. CPU, SRAM, Program Memory and Data DD Memory are operational. No peripheral modules are operating. © 2008 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40° ...
Page 150
... MIPS LPRC (512 kHz) (1.8 MIPS) FRC (7.37 MHz) 4 MIPS 10 MIPS 20 MIPS 30 MIPS © 2008 Microchip Technology Inc. ...
Page 151
... LVD, BOR, WDT, etc. are all switched off. The Δ current is the additional current consumed when the module is enabled. This current should be 3: added to the base I current. PD © 2008 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40° ...
Page 152
... SM bus disabled bus enabled bus disabled V SM bus enabled μ 5V PIN SS μA ≤ V ≤ PIN DD Pin at high impedance μA ≤ V ≤ PIN DD Pin at high impedance μA ≤ V ≤ PIN DD μA ≤ V ≤ XT PIN DD and LP Osc mode © 2008 Microchip Technology Inc. ...
Page 153
... Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: These parameters are characterized but not tested in manufacturing. © 2008 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) ...
Page 154
... Typ Max Units Conditions — — V — — V — — V — — V — 2.65 V — 2.86 V — 2.97 V — 3.18 V — 3.50 V — 3.71 V — 3.82 V — 4.03 V — 4.24 V — 4.45 V — 4.77 V — — V © 2008 Microchip Technology Inc. ...
Page 155
... Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: These parameters are characterized but not tested in manufacturing values not in usable operating range. © 2008 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 BO15 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40° ...
Page 156
... T ≤ +85°C A Using EECON to Read/Write V = Minimum operating MIN voltage Provided no other specifications are violated Row Erase -40°C ≤ T ≤ +85° Minimum operating MIN voltage Provided no other specifications are violated Row Erase Bulk Erase © 2008 Microchip Technology Inc. ...
Page 157
... LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 — for all pins except OSC2 Pin FIGURE 20-4: EXTERNAL CLOCK TIMING Q4 OSC1 CLKO © 2008 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40°C ≤ T Operating voltage V range as described in Section 20.1 “ ...
Page 158
... MHz FRC internal MHz FRC internal w/4x PLL MHz FRC internal w/8x PLL MHz FRC internal w/16x PLL kHz LPRC internal — See parameter OS10 for F value OSC ns See Table 20- See parameter DO31 ns See parameter DO32 ). CY © 2008 Microchip Technology Inc. ...
Page 159
... Operating temperature Param Characteristic No. OS61 x4 PLL x8 PLL x16 PLL Note 1: These parameters are characterized but not tested in manufacturing. © 2008 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 = 2 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40°C ≤ T (1) ...
Page 160
... CY * PLLx)/4 [since there are 4 Q clocks per instruction OSC (3) (3) MIPS MIPS w PLL x8 w PLL x16 — — 8.0 16.0 20.0 — — — 8.0 16.0 20.0 — © 2008 Microchip Technology Inc. ...
Page 161
... TABLE 20-19: AC CHARACTERISTICS: INTERNAL LPRC ACCURACY AC CHARACTERISTICS Param Characteristic No. (1) LPRC @ Freq. = 512 kHz OS65A OS65B OS65C Note 1: Change of LPRC frequency as V © 2008 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 -40°C ≤ T -40°C ≤ T Min Typ Max Units (1) -40°C ≤ T — — ...
Page 162
... Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T ≤ +85°C for Industrial Operating temperature A -40°C ≤ T ≤ +125°C for Extended A (1)(2)(3) (4) Min Typ Max — — — — — — CY Units Conditions OSC © 2008 Microchip Technology Inc. ...
Page 163
... These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. 3: Refer to Figure 20-2 and Table 20-11 for BOR. © 2008 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 SY10 SY13 Note: Refer to Figure 20-3 for load conditions. ...
Page 164
... Band Gap Stable ≤ +85°C for Industrial A ≤ +125°C for Extended A Conditions Defined as the time between the instant that the band gap is enabled and the moment that the band gap reference voltage is stable. RCON<13> bit © 2008 Microchip Technology Inc. ...
Page 165
... TCS (T1CON, bit 1)) TA20 T Delay from External TxCK Clock CKEXTMRL Edge to Timer Increment Note: Timer1 is a Type A. © 2008 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Tx11 Tx10 Tx15 OS60 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature ...
Page 166
... T — CY ≤ +85°C for Industrial A ≤ +125°C for Extended A Max Units Conditions — ns Must also meet parameter TC15 — ns Must also meet parameter TC15 — prescale value (1, 8, 64, 256) 1.5 — © 2008 Microchip Technology Inc. ...
Page 167
... IC11 TccH ICx Input High Time IC15 TccP ICx Input Period Note 1: These parameters are characterized but not tested in manufacturing. © 2008 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 IC10 IC11 IC15 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40° ...
Page 168
... T Operating temperature -40°C ≤ T (1) (2) Min Typ Max — — — — — — ≤ +85°C for Industrial A ≤ +125°C for Extended A Units Conditions ns See Parameter DO32 ns See Parameter DO31 © 2008 Microchip Technology Inc. ...
Page 169
... These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. © 2008 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 OC20 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) ...
Page 170
... T ≤ +125°C for Extended A Max Units Conditions — ns — — ns — — ns See parameter DO32 — ns See parameter DO31 — ns See parameter DO32 — ns See parameter DO31 30 ns — — ns — — ns — © 2008 Microchip Technology Inc. ...
Page 171
... Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: The minimum clock period for SCK is 100 ns. Therefore, the clock generated in master mode must not violate this specification. 4: Assumes 50 pF load on all SPI pins. © 2008 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 SP10 SP21 SP35 SP20 BIT ...
Page 172
... Industrial A -40°C ≤ T ≤ +125°C for Extended A Max Units Conditions — ns — — ns — — — — ns See DO32 — ns See DO31 30 ns — — ns — — ns — — ns — — — ns — © 2008 Microchip Technology Inc. ...
Page 173
... SCK X (CKP = 0) SP71 SCK X (CKP = 1) MSb SDO X SDI SDI X MSb IN SP41 SP40 Note: Refer to Figure 20-3 for load conditions. © 2008 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 SP70 SP73 SP35 SP72 SP52 BIT LSb SP30,SP31 BIT LSb IN SP52 SP72 SP73 SP51 DS70139F-page 173 ...
Page 174
... T ≤ +125°C for Extended A Max Units Conditions — ns — — ns — — — — ns See parameter DO32 — ns See parameter DO31 30 ns — — ns — — ns — — ns — — — ns — — © 2008 Microchip Technology Inc. ...
Page 175
... FIGURE 20-17: I C™ BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM20 SCL IM11 IM10 SDA In IM40 SDA Out Note: Refer to Figure 20-3 for load conditions. © 2008 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 IM11 IM10 IM26 IM25 IM40 IM34 IM33 Stop Condition IM21 IM33 ...
Page 176
... C™ pins (for 1 MHz mode only). © 2008 Microchip Technology Inc. ≤ +85°C for Industrial A ≤ +125°C for Extended A Conditions C is specified from 10 to 400 specified from 10 to 400 pF ...
Page 177
... F SCL Fall Time IS21 T : SDA and SCL R SCL Rise Time Note 1: Maximum pin capacitance = 10 pF for all I © 2008 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 IS11 IS10 IS26 IS25 IS40 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature A -40°C ≤ T ...
Page 178
... Only relevant for Repeated Start condition μs μs μs After this period the first clock pulse is generated μs μs μs μs μ μs Time the bus must be free before a new transmission μs can start μs pF © 2008 Microchip Technology Inc. ...
Page 179
... These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. © 2008 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 CA10 CA11 CA20 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40° ...
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... See Note 1 V — INL SS REFL 0V REFH Source Impedance = 2.5 kΩ INL SS REFL 0V REFH Source Impedance = 2.5 kΩ Ω Ω INL SS REFL 0V REFH INL SS REFL 0V REFH INL SS REFL 0V REFH INL SS REFL 0V REFH INL SS REFL 0V REFH INL SS REFL 0V REFH © 2008 Microchip Technology Inc. ...
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... Effective Number of Bits Note 1: The A/D conversion result never decreases with an increase in the input voltage, and has no missing codes. 2: Measurements taken with external V © 2008 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40° ...
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... Section 18. “12-bit A/D Converter” in the dsPIC30F Family Reference Manual (DS70046). SAMP 3 - Software clears ADCON. SAMP to Start conversion Sampling ends, conversion sequence starts Convert bit 11 Convert bit 10 Convert bit Convert bit One T for end of conversion. AD DS70139F-page 182 AD55 © 2008 Microchip Technology Inc. ...
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... ADC module to stabilize when it is turned on (ADCON1<ADON> = 1). DPU During this time the ADC result is indeterminate. © 2008 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Standard Operating Conditions: 2.7V to 5.5V (unless otherwise stated) Operating temperature-40°C ≤ T Min. ...
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... NOTES: DS70139F-page 184 © 2008 Microchip Technology Inc. ...
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... Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2008 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Example dsPIC30F3012 30I/P Example dsPIC30F2011 30I/SO e 0610017 Example ...
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... Package Marking Information (Continued) 28-Lead SOIC (.300”) XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX YYWWNNN 28-Lead QFN XXXXXXX XXXXXXX YYWWNNN 44-Lead QFN XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN DS70139F-page 186 Example dsPIC30F3013 e 30I/SO 3 0610017 Example 30F2011 30I/ 0610017 Example dsPIC 30F3013 e 30I/ML 3 0610017 © 2008 Microchip Technology Inc. ...
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... Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 DS70139F-page 187 ...
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... DS70139F-page 188 α φ β © 2008 Microchip Technology Inc. ...
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... Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 DS70139F-page 189 ...
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... DS70139F-page 190 α φ β © 2008 Microchip Technology Inc. ...
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... Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 DS70139F-page 191 ...
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... DS70139F-page 192 © 2008 Microchip Technology Inc. ...
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... Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 DS70139F-page 193 ...
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... NOTES: DS70139F-page 194 © 2008 Microchip Technology Inc. ...
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... Watchdog Timer time-out limits (see Table 20-21) Revision E (December 2006) This revision includes updates to the packaging diagrams. © 2008 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Revision F (May 2008) This revision reflects these updates: • Added FUSE Configuration Register (FICD) details (see Section 17.7 “Device Configuration Registers” ...
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... NOTES: DS70139F-page 196 © 2008 Microchip Technology Inc. ...
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... ADC Functional............................................... 111 16-bit Timer1 Module .................................................. 73 16-bit Timer2............................................................... 79 16-bit Timer3............................................................... 79 32-bit Timer2/3............................................................ 78 DSP Engine ................................................................ 24 dsPIC30F2011 ............................................................ 12 dsPIC30F2012 ............................................................ 13 dsPIC30F3013 ............................................................ 15 External Power-on Reset Circuit............................... 129 © 2008 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 .............................................................................. 96 Input Capture Mode.................................................... 83 Oscillator System...................................................... 123 Output Compare Mode ............................................... 87 Reset System ........................................................... 127 Shared Port Structure................................................. 59 SPI ...
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... Input Capture Timing Requirements................................. 167 Input Change Notification Module....................................... 63 dsPIC30F2012/3013 Register Map (Bits 7-0)............. 63 Instruction Addressing Modes ............................................ 43 File Register Instructions ............................................ 43 Fundamental Modes Supported ................................. 43 MAC Instructions ........................................................ 44 MCU Instructions ........................................................ 43 Move and Accumulator Instructions............................ 44 Other Instructions ....................................................... 44 Instruction Set Overview................................................................... 138 Summary .................................................................. 135 © 2008 Microchip Technology Inc. ...
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... Output Compare Module..................................................... 87 Register Map............................................................... 90 Timing Characteristics .............................................. 168 Timing Requirements................................................ 168 Output Compare Operation During CPU Idle Mode............ 89 Output Compare Sleep Mode Operation ............................ 89 © 2008 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 P Packaging Information ...................................................... 185 Marking............................................................. 185, 186 Peripheral Module Disable (PMD) Registers .................... 133 PICSTART Plus Development Programmer ...
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... Timing Diagrams.See Timing Characteristics Timing Requirements A/D Conversion Low-speed ........................................................ 183 Bandgap Start-up Time............................................. 164 Brown-out Reset ....................................................... 163 CAN Module I/O........................................................ 179 CLKOUT and I/O ...................................................... 162 External Clock........................................................... 158 Bus Data (Master Mode) .................................... 176 Bus Data (Slave Mode) ...................................... 177 © 2008 Microchip Technology Inc. ...