DSPIC30F3012-20I/SO Microchip Technology, DSPIC30F3012-20I/SO Datasheet - Page 87

• Manufacturer Part Number: DSPIC30F3012-20I/SO
• Description: IC DSPIC MCU/DSP 24K 18SOIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F3012-20I/SO

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 12
• Program Memory Size: 24KB (8K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 18-SOIC (7.5mm Width)
• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 12
• Flash Memory Size: 24KB
• Supply Voltage Range: 2.5V To 5.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT18SO-1 - SOCKET TRANSITION 18SOIC 300MILAC30F005 - MODULE SCKT DSPIC30F 18DIP/SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: DSPIC30F301220ISO

12.0
This section describes the output compare module and
associated operational modes. The features provided
by this module are useful in applications requiring
operational modes, such as:
• Generation of Variable Width Output Pulses
• Power Factor Correction
FIGURE 12-1:
© 2008 Microchip Technology Inc.
Note:
Note:
OUTPUT COMPARE MODULE
From GP
Timer Module
This data sheet summarizes features of
this group of dsPIC30F devices and is not
intended to be a complete reference
source. For more information on the CPU,
peripherals, register descriptions and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046).
TMR2<15:0
Where ‘x’ is shown, reference is made to the registers associated with the respective output compare
channel (1 or 2).
0
OUTPUT COMPARE MODE BLOCK DIAGRAM
Comparator
OCxRS
OCxR
TMR3<15:0>
dsPIC30F2011/2012/3012/3013
1
OCTSEL
T2P2_MATCH
0
Figure 12-1 depicts a block diagram of the output
compare module.
The key operational features of the output compare
module include:
• Timer2 and Timer3 Selection mode
• Simple Output Compare Match mode
• Dual Output Compare Match mode
• Simple PWM mode
• Output Compare During Sleep and Idle modes
• Interrupt on Output Compare/PWM Event
These operating modes are determined by setting the
appropriate bits in the 16-bit OC1CON and OC2CON
registers. The dsPIC30F2011/2012/3012/3013 devices
have 2 compare channels.
OCxRS and OCxR in Figure 12-1 represent the Dual
T3P3_MATCH
Mode Select
OCM<2:0>
1
Output
3
Logic
Set Flag bit
OCxIF
S
R
Q
Output
Enable
(for x = 1, 2, 3 or 4)
OCFA
OCx
DS70139F-page 87