DSPIC30F3011-30I/PT Microchip Technology, DSPIC30F3011-30I/PT Datasheet - Page 15

IC DSPIC MCU/DSP 24K 44TQFP

DSPIC30F3011-30I/PT

Manufacturer Part Number
DSPIC30F3011-30I/PT
Description
IC DSPIC MCU/DSP 24K 44TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr

Specifications of DSPIC30F3011-30I/PT

Program Memory Type
FLASH
Program Memory Size
24KB (8K x 24)
Package / Case
44-TQFP, 44-VQFP
Core Processor
dsPIC
Core Size
16-Bit
Speed
30 MIPs
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
30
Eeprom Size
1K x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC30F
Core
dsPIC
Maximum Clock Frequency
30 MHz
Data Ram Size
1024 B
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM330011, DM300018
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC30F006 - MODULE SKT FOR DSPIC30F 44TQFPAC164305 - MODULE SKT FOR PM3 44TQFPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
DSPIC30F301130IPT

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Quantity
Price
Part Number:
DSPIC30F3011-30I/PT
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DSPIC30F3011-30I/PT
Manufacturer:
Microchip Technology
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DSPIC30F3011-30I/PT
0
21. Module: I
22. Module: I/O Port
23. Module: ADC
© 2010 Microchip Technology Inc.
If there are two I
them is acting as the Master receiver and the other
as the Slave transmitter. If both devices are config-
ured for 10-bit addressing mode, and have the
same value in the A10 and A9 bits of their
addresses, then when the Slave select address is
sent from the Master, both the Master and Slave
acknowledge it. When the Master sends out the
read operation, both the Master and the Slave
enter into Read mode and both of them transmit
the data. The resultant data will be the ANDing of
the two transmissions.
Work around
In all I
A10 and A9 should be different.
Affected Silicon Revisions
If the user application enables the auto-baud
feature in the UART module, the I/O pin
multiplexed with the IC1 (Input Capture) pin cannot
be used as a digital input. However, the external
interrupt function (INT1) can be used.
Work around
None.
Affected Silicon Revisions
If the user application uses the internal reference
voltage (AV
greater than what is specified in the device data
sheet.
Work around
As an alternative, use the external reference
voltage (V
Affected Silicon Revisions
A0
A0
A0
X
X
X
2
C devices, the addresses as well as bits
A1
A1
A1
X
X
X
REF
DD
2
C
-, V
A2
A2
, AV
A2
X
X
X
REF
2
SS
C devices on the bus, one of
), the ADC has an offset error
+).
24. Module: PWM
25. Module: Timer
26. Module: PLL
If the PTDIR bit is set (when PTMR is counting
down), and the CPU execution is halted (after a
breakpoint is reached), PTMR will start counting
up as if PTDIR was zero.
Work around
None.
Affected Silicon Revisions
When the timer is being operated in Asynchronous
mode using the secondary oscillator (32.768 kHz)
and the device is put into Sleep mode, a clock
switch to any other oscillator mode before putting
the device to Sleep prevents the timer from waking
the device from Sleep.
Work around
Do not clock switch to any other oscillator mode if
the timer is being used in Asynchronous mode
using the secondary oscillator (32.768 kHz).
Affected Silicon Revisions
The PLL LOCK Status bit (OSCCON<5>) can
occasionally get cleared and generate an
oscillator failure trap even when the PLL is still
locked and functioning correctly.
Work around
The user application must include an oscillator
failure Trap Service Routine (TSR). In the trap
service routine, first inspect the status of the Clock
Failure Status bit (OSCCON<3>). If this bit is clear,
return from the trap service routine immediately
and continue program execution.
Affected Silicon Revisions
A0
A0
A0
X
X
X
A1
A1
A1
dsPIC30F3010/3011
X
X
X
A2
A2
A2
X
X
X
DS80449D-page 15

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