DSPIC30F3011-30I/PT Microchip Technology, DSPIC30F3011-30I/PT Datasheet - Page 3

• Manufacturer Part Number: DSPIC30F3011-30I/PT
• Description: IC DSPIC MCU/DSP 24K 44TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F3011-30I/PT

• Program Memory Type: FLASH
• Program Memory Size: 24KB (8K x 24)
• Package / Case: 44-TQFP, 44-VQFP
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 30
• Eeprom Size: 1K x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC30F
• Core: dsPIC
• Maximum Clock Frequency: 30 MHz
• Data Ram Size: 1024 B
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM330011, DM300018
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC30F006 - MODULE SKT FOR DSPIC30F 44TQFPAC164305 - MODULE SKT FOR PM3 44TQFPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: DSPIC30F301130IPT

TABLE 2:
© 2010 Microchip Technology Inc.
Note 1:
Module
I/O Port
I
PWM
Timer
Sleep
Mode
ADC
ADC
2
PLL
QEI
QEI
I
I
I
I
C™
2
2
2
2
C
C
C
C
Only those issues indicated in the last column apply to the current silicon revision.
in Sleep Mode
(AV
Accumulation
Accumulation
Consumption
Bus Collision
Timer Gated
Timer Gated
When Using
Slave Mode
Sleep Mode
Offset Error
Addressing
Addressing
Addressing
Multiplexed
Reference
SILICON ISSUE SUMMARY (CONTINUED)
PLL Lock
Status bit
Register
Feature
Port Pin
with IC1
Counter
Internal
Current
DD
10-bit
Mode
10-bit
Mode
10-bit
Mode
Mode
Mode
—
, AV
SS
)
Number
Item
17.
18.
19.
20.
21.
22.
23.
24.
25.
26.
27.
28.
29.
30.
When the I
generates a glitch on the SDA and SCL pins, causing a false
communication start in a single-master configuration or a bus
collision in a multi-master configuration.
The 10-bit slave does not set the RBF flag or load the
I2CxRCV register on address match if the Least Significant
bits (LSbs) of the address are the same as the 7-bit reserved
addresses.
The I
an I
When the I
address of 0x102, the I2CxRCV register content for the lower
address byte is 0x01 rather than 0x02.
When the I
the same address bits (A10 and A9) as other I
A10 and A9 bits may not work as expected.
The port I/O pin multiplexed with the Input Capture 1 (IC1)
function cannot be used as a digital input pin when the UART
auto-baud feature is enabled.
The ADC module has an offset error (greater than the
specification mentioned in the device data sheet), when using
an internal reference (AV
PTMR does not continue counting down after halting code
execution in Debug mode.
Clock switching prevents the device from waking up from
Sleep.
The PLL LOCK Status bit (OSCCON<5>) can occasionally get
cleared and generate an Oscillator Failure Trap even when the
PLL is still locked and functioning correctly.
Execution of the Sleep instruction (PWRSAV #0) may cause
incorrect program operation after the device wakes up from
Sleep. The current consumption during Sleep may also
increase beyond the specifications listed in the device data
sheet.
When Timer Gated Accumulation is enabled, the QEI does not
generate an interrupt on every falling edge.
When Timer Gated Accumulation is enabled, and an external
signal is applied, the POSCNT increments and generates an
interrupt after a match with MAXCNT.
If the ADC module is in an enabled state when the device
enters Sleep Mode, the power-down current (I
may exceed the device data sheet specifications.
2
C slave.
2
C module loses incoming data bytes when operating as
2
2
2
C module is configured for 10-bit addressing using
C module is enabled, the dsPIC
C module is configured as a 10-bit slave with an
Issue Summary
DD
, AV
SS
).
dsPIC30F3010/3011
®
PD
DSC device
2
C devices, the
) of the device
DS80449D-page 3
Revisions
A0 A1 A2
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Affected
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
(1)