ATMEGA16L-8AU Atmel, ATMEGA16L-8AU Datasheet - Page 240

• Manufacturer Part Number: ATMEGA16L-8AU
• Description: IC AVR MCU 16K 8MHZ 3V 44TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA16L-8AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Processor Series: ATMEGA16x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: JTAG/SPI/UART
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• For Use With: ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2466T–AVR–07/10
•
As an example, consider the task of verifying a 1.5V ±5% input signal at ADC channel 3 when
the power supply is 5.0V and AREF is externally connected to V
The recommended values from
in
“Actions” describes what JTAG instruction to be used before filling the Boundary-scan Register
with the succeeding columns. The verification should be done on the data scanned out when
scanning in the data on the same row in the table.
Table 93. Algorithm for Using the ADC
Using this algorithm, the timing constraint on the HOLD signal constrains the TCK clock fre-
quency. As the algorithm keeps HOLD high for five steps, the TCK clock frequency has to be at
least five times the number of scan bits divided by the maximum hold time, t
Step
10
11
Table
1
2
3
4
5
6
7
8
9
controlling/observing any ADC signal, or perform a dummy conversion before using the first
result.
The DAC values must be stable at the midpoint value 0x200 when having the HOLD signal
low (Sample mode).
Actions
SAMPLE
_PRELO
AD
EXTEST
Verify the
COMP bit
scanned
out to be
0
Verify the
COMP bit
scanned
out to be
1
93. Only the DAC and Port Pin values of the Scan-chain are shown. The column
The lower limit is:
The upper limit is:
ADCEN
1
1
1
1
1
1
1
1
1
1
1
DAC
0x200
0x200
0x200
0x123
0x123
0x200
0x200
0x200
0x143
0x143
0x200
Table 92
MUXEN
0x08
0x08
0x08
0x08
0x08
0x08
0x08
0x08
0x08
0x08
0x08
1024 1,5V 0,95 5V
1024 1,5V 1,05 5V
are used unless other values are given in the algorithm
⋅
⋅
HOLD
1
0
1
1
1
1
0
1
1
1
1
⋅
⋅
PRECH
⁄
⁄
1
1
1
1
0
1
1
1
1
0
1
=
=
291
323
PA3.
Data
CC
0
0
0
0
0
0
0
0
0
0
0
.
=
=
0x123
0x143
ATmega16(L)
PA3.
Control
0
0
0
0
0
0
0
0
0
0
0
hold,max
PA3.
Pullup_
Enable
.
0
0
0
0
0
0
0
0
0
0
0
240