ATMEGA162-16PU Atmel, ATMEGA162-16PU Datasheet - Page 93

• Manufacturer Part Number: ATMEGA162-16PU
• Description: IC AVR MCU 16K 16MHZ 5V 40DIP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA162-16PU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Processor Series: ATMEGA16x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: JTAG/SPI/USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• Cpu Speed: 16 MIPS
• Eeprom Memory: 512 Bytes
• Input Output: 35
• Interface: JTAG/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin PDIP
• Programmable Memory: 16K Bytes
• Timers: 2-8-bit, 2-16-bit
• Voltage, Range: 2.7-5.5 V
• Package: 40PDIP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 16 MHz
• For Use With: ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Using the Output
Compare Unit
Compare Match
Output Unit
2513K–AVR–07/09
Since writing TCNT0 in any mode of operation will block all compare matches for one timer clock
cycle, there are risks involved when changing TCNT0 when using the output compare channel,
independently of whether the Timer/Counter is running or not. If the value written to TCNT0
equals the OCR0 value, the Compare Match will be missed, resulting in incorrect waveform gen-
eration. Similarly, do not write the TCNT0 value equal to BOTTOM when the counter is down-
counting.
The setup of the OC0 should be performed before setting the Data Direction Register for the port
pin to output. The easiest way of setting the OC0 value is to use the Force Output Compare
(FOC0) strobe bits in Normal mode. The OC0 Register keeps its value even when changing
between Waveform Generation modes.
Be aware that the COM01:0 bits are not double buffered together with the compare value.
Changing the COM01:0 bits will take effect immediately.
The Compare Output mode (COM01:0) bits have two functions. The Waveform Generator uses
the COM01:0 bits for defining the Output Compare (OC0) state at the next Compare Match.
Also, the COM01:0 bits control the OC0 pin output source.
matic of the logic affected by the COM01:0 bit setting. The I/O Registers, I/O bits, and I/O pins in
the figure are shown in bold. Only the parts of the general I/O Port Control Registers (DDR and
PORT) that are affected by the COM01:0 bits are shown. When referring to the OC0 state, the
reference is for the internal OC0 Register, not the OC0 pin. If a System Reset occur, the OC0
Register is reset to “0”.
Figure 36. Compare Match Output Unit, Schematics
The general I/O port function is overridden by the Output Compare (OC0) from the waveform
generator if either of the COM01:0 bits are set. However, the OC0 pin direction (input or output)
is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction Regis-
ter bit for the OC0 pin (DDR_OC0) must be set as output before the OC0 value is visible on the
pin. The port override function is independent of the Waveform Generation mode.
COMn1
COMn0
FOCn
clk
I/O
Waveform
Generator
D
D
D
PORT
OCn
DDR
Q
Q
Q
Figure 36
1
0
ATmega162/V
shows a simplified sche-
OCn
Pin
93