ATMEGA162-16PU Atmel, ATMEGA162-16PU Datasheet - Page 97

IC AVR MCU 16K 16MHZ 5V 40DIP

ATMEGA162-16PU

Manufacturer Part Number
ATMEGA162-16PU
Description
IC AVR MCU 16K 16MHZ 5V 40DIP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA162-16PU

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Processor Series
ATMEGA16x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
JTAG/SPI/USART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
35
Number Of Timers
4
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
Cpu Speed
16 MIPS
Eeprom Memory
512 Bytes
Input Output
35
Interface
JTAG/SPI/USART
Memory Type
Flash
Number Of Bits
8
Package Type
44-pin PDIP
Programmable Memory
16K Bytes
Timers
2-8-bit, 2-16-bit
Voltage, Range
2.7-5.5 V
Package
40PDIP
Device Core
AVR
Family Name
ATmega
Maximum Speed
16 MHz
For Use With
ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
2513K–AVR–07/09
has lower maximum operation frequency than single slope operation. However, due to the sym-
metric feature of the dual-slope PWM modes, these modes are preferred for motor control
applications.
The PWM resolution for the phase correct PWM mode is fixed to eight bits. In phase correct
PWM mode the counter is incremented until the counter value matches MAX. When the counter
reaches MAX, it changes the count direction. The TCNT0 value will be equal to MAX for one
timer clock cycle. The timing diagram for the phase correct PWM mode is shown on
The TCNT0 value is in the timing diagram shown as a histogram for illustrating the dual-slope
operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal
line marks on the TCNT0 slopes represent compare matches between OCR0 and TCNT0.
Figure 39. Phase Correct PWM Mode, Timing Diagram
The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. The
Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM
value.
In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the
OC0 pin. Setting the COM01:0 bits to two will produce a non-inverted PWM. An inverted PWM
output can be generated by setting the COM01:0 to three (See
actual OC0 value will only be visible on the port pin if the data direction for the port pin is set as
output. The PWM waveform is generated by clearing (or setting) the OC0 Register at the Com-
pare Match between OCR0 and TCNT0 when the counter increments, and setting (or clearing)
the OC0 Register at Compare Match between OCR0 and TCNT0 when the counter decrements.
The PWM frequency for the output when using phase correct PWM can be calculated by the fol-
lowing equation:
The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
TCNTn
OCn
OCn
Period
1
f
OCnPCPWM
2
=
----------------- -
N 510
f
clk_I/O
3
Table 50 on page
ATmega162/V
OCn Interrupt Flag Set
OCRn Update
TOVn Interrupt Flag Set
(COMn1:0 = 2)
(COMn1:0 = 3)
Figure
101). The
39.
97

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