DSPIC33FJ128GP706A-I/MR Microchip Technology, DSPIC33FJ128GP706A-I/MR Datasheet - Page 37

• Manufacturer Part Number: DSPIC33FJ128GP706A-I/MR
• Description: IC DSPIC MCU/DSP 128K 64-QFN
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ128GP706A-I/MR

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 18x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Product: DSCs
• Processor Series: DSPIC33F
• Core: dsPIC
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
• Core Frequency: 40MHz
• Core Supply Voltage: 3.3V
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 53
• Flash Memory Size: 128KB
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

3.6
TABLE 3-1:
3.7
TABLE 3-2:
© 2009 Microchip Technology Inc.
Interrupt
Sync Field
Timer
Resource Name
System Clock
2 bytes
COMMUNICATION OF UART INTERFACE
RESOURCE CONFIGURATION
SPI2
SPI1
UART RX
UART TX
FRAME STRUCTURE OF COMMUNICATION PROTOCOL
CONFIGURATION OF MCU RESOURCES
Timer2
Timer3
TMR2
ADC
IC1
Command Type
The UART interface is used to communicate with the upper computer (MCU or PC). Via
the UART interface, the upper computer reads the measured parameters of the power
grid, and may also send system parameters and calibration parameters to the target
board as well.
The communication interface is a bidirectional interface based on UART, using
master/slave half-duplex mode. The baud rate is 19,200 bps, with 1 start bit, 8 data bits
and 1 stop bit. Communication is done by frames with non-fixed-length frame structure,
definition of which is shown in Table 3-1. The Communication protocol is specified in a
master-slave structure. The system in this design is the slave, and the upper computer
is the master. The master sends commands to the slave, and slave responds to the
master.
Each command is defined in Chapter 6. “Meter Communications Protocol”.
Details of the MCU resources used in this design and their configurations are listed in
Table 3-2.
1 byte
Interrupt
Priority
none
none
none
1
1
5
2
2
2
Fcy = 29.4912M, provided by an external 7.3728 Mz timer through an inter-
nal PLL frequency doubler.
System clock, used for timing. Its cycle is 10 ms. The interrupt flag may be
set in the IRS. Used to extend the indication of timer. Also used to deal with
UART reception overtime.
Used to detect ADC's sampling synchronization of neutral current. After the
frequency of the power grid is measured, the period of TMR3 is adjusted
accordingly. 16 points are sampled by ADC for each cycle of power grid.
ditto
Driven by a 3.2768 MHz clock. The MCP3909 device can generate
12.8 ksps of data output.
Sampling input capture. An interrupt is generated for every two MCP3909
device samplings. 6.4 ksps sampling rate is realized.
In fact, active power is cumulated at 6.4 ksps sampling rate (128 sampling
points each cycle at 50 Hz), but other parameters are cumulated at 3.2 ksps
sampling rate
Receive data of UART communication
Transmit data of UART communication
Detect current of neutral line
Used in communicating with the MCP390X device - set the MCP390X
device's modes and read A/D results
Unused, but the interface is reserved and may be used to communicate
with upper computer in substitution of the UART interface
Data Length
1 byte
Data Field
N bytes
Functional Description
Checkout Byte
1 byte
Firmware
DS51723A-page 37
End Byte
1 byte