DSPIC33FJ128GP706A-I/MR Microchip Technology, DSPIC33FJ128GP706A-I/MR Datasheet - Page 98

• Manufacturer Part Number: DSPIC33FJ128GP706A-I/MR
• Description: IC DSPIC MCU/DSP 128K 64-QFN
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ128GP706A-I/MR

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 18x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Product: DSCs
• Processor Series: DSPIC33F
• Core: dsPIC
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
• Core Frequency: 40MHz
• Core Supply Voltage: 3.3V
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 53
• Flash Memory Size: 128KB
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

MCP3909 / dsPIC33F 3-Phase Energy Meter Reference Design
C.16 PHASE LAG COMPENSATION
DS51723A-page 98
Phase lag of a CT has no effect on the metering of RMS current/voltage and apparent
power, but will affect the metering of power, since the phase lag will change the phase
relationship between the input current and the voltage. This will result in a deviation of
the calculated active power from the calculated reactive power.
Figure C-10 shows how a transformer's phase lag affects the measured results under
both inductive and capacitive loads. Let's assume that the output of CT has no phase
lag from the input voltage, while the CT has a phase lag from the input signal. With
inductive loads, the phase angle increases between the volatge and the current
because of the phase lag induced by the CT, resulting in a decrease of the measured
active power and an increase of the reactive power. While with capacitive loads, the
phase angle between the voltage and the current decreases because of the phase lag
induced by the CT, resulting in a decrease of the measured reactive power and an
increase of active power.
There are many methods for phase lag compensation. In this design the result correc-
tion method is used. It compensates with a coefficient after the active power and
reactive power are figured out, which has a small amount of calculation.
FIGURE C-10:
Assuming that the phase lag of CT is ϕ
phase lag between current and voltage is:
FIGURE C-11:
Inductive
Capacitive
Load
Load
θ
Δθ
Measurement Change Caused By Transformer Phase Lag.
Principle Of Phase Lag Correction.
Δf
CT Output
current
current
voltage
Input
Input
F
S
P'
P
i
, of PT is ϕ
Δϕ
=
ϕ
u
–
u
, after PT and CT, the variation of
ϕ
Inductive
Capacitive
i
.
Load
Load
Q
© 2009 Microchip Technology Inc.
θ
Q'
Δθ
current
Input
voltage
Input
CT Output
current