DSPIC33FJ128GP708-I/PT Microchip Technology, DSPIC33FJ128GP708-I/PT Datasheet - Page 3

• Manufacturer Part Number: DSPIC33FJ128GP708-I/PT
• Description: IC DSPIC MCU/DSP 128K 80TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ128GP708-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 128KB (128K x 8)
• Package / Case: 80-TFQFP
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 69
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 24x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC33F
• Core: dsPIC
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 69
• Data Ram Size: 16 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1001 - DSPIC33 BREAKOUT BOARDDM300024 - KIT DEMO DSPICDEM 1.1DV164033 - KIT START EXPLORER 16 MPLAB ICD2MA330012 - MODULE DSPIC33 100P TO 84QFPMA330011 - MODULE DSPIC33 100P TO 100QFPDM300019 - BOARD DEMO DSPICDEM 80L STARTERDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32AC164328 - MODULE SKT FOR 80TQFPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

TABLE 2:
© 2010 Microchip Technology Inc.
Note 1:
Controller
Regulator
Device ID
Oscillator
Compare
Interrupt
Register
Module
Internal
Voltage
Output
ECAN
UART
UART
UART
UART
UART
UART
UART
Mode
JTAG
Doze
DMA
DMA
ADC
SPI
I
I
I
2
2
2
C
C
C
Only those issues indicated in the last column apply to the current silicon revision.
Programming
Match Mode
Sleep Mode
High-Speed
High-Speed
Slave Mode
Slave Mode
Sleep Mode
Doze Mode
Idle Modes
Auto-Baud
Auto-Baud
Sleep and
Idle Mode
Accuracy
Compare
Overflow
SDI1 Pin
SILICON ISSUE SUMMARY (CONTINUED)
Feature
Receive
Mode
Mode
Flash
FRC
Dual
—
—
—
—
—
—
Number
Item
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
25.
26.
27.
28.
29.
30.
31.
32.
33.
34.
35.
ADC event triggers from the INT0 pin will not wake-up the
device from Sleep or Idle mode if the SMPI bits are non-zero.
The address error trap, stack error trap, math error trap and
DMA error trap will not wake-up a device from Doze mode.
JTAG programming does not work.
With the parity option enabled, a parity error may occur if the
Baud Rate Generator (BRG) contains an odd value.
The Receive Buffer Overrun Error Status bit may get set
before the UART FIFO has overflowed.
UART receptions may be corrupted if the BRG is set up for 4x
mode.
The UTXISEL0 bit is always read back as zero.
The auto-baud feature may not calculate the correct baud rate
when the BRG is set up for 4x mode.
With the auto-baud feature selected, the Sync Break character
(0x55) may be loaded into the FIFO as data.
A write collision does not prevent the transmit register from
being written.
The ACKSTAT bit only reflects the received ACK/NACK status
for Master transmissions, but not for Slave transmissions.
The D_A Status bit does not get set on a slave write to the
transmit register.
If a clock failure occurs when the device is in Idle mode, the
oscillator failure trap does not vector to the Trap Service
Routine (TSR).
An MCLR wake-up from Sleep mode does not wait for the on-chip
voltage regulator to power-up.
The C1RXOVF2 and C2RXOVF2 registers always read back
as 0x0000.
Internal FRC accuracy parameters are not within the
published data sheet specifications.
SPI1 functionality for pin 34 (U1RX/SDI1/RF2) is erroneously
enabled by the SPI2 module.
The auto-baud feature measures baud rate inaccurately for
certain baud rate and clock speed combinations.
The content of the Device ID register changes from the factory
programmed value.
DMA data transfers that are active in Single-Shot mode while
the device is in Sleep or Idle mode may result in more data
transfers than expected.
A DMA error trap may not be generated when the device is in
Doze mode.
In Dual Compare Match mode, the OCx output is not reset
when the OCxR and OCxRS registers are loaded with values
having a difference of 1.
Issue Summary
DS80446D-page 3
Revisions
A2 A3 A4
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(1)
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