PIC18F442-I/L Microchip Technology, PIC18F442-I/L Datasheet - Page 60

• Manufacturer Part Number: PIC18F442-I/L
• Description: IC MCU FLASH 8KX16 EE A/D 44PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F442-I/L

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• Controller Family/series: PIC18
• No. Of I/o's: 34
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 768Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: MSSP, SPI, I2C, PSP, USART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163022, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8
• Package: 44PLCC
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164309 - MODULE SKT FOR PM3 44PLCCXLT44L2 - SOCKET TRAN ICE 44PLCC444-1001 - DEMO BOARD FOR PICMICRO MCUDVA16XL441 - ADAPTER DEVICE ICE 44PLCCDV007003 - PROGRAMMER UNIVERSAL PROMATE II
• Lead Free Status / Rohs Status: Details
• Other names: PIC18F442I/L

PIC18FXX2
5.2.2
The Table Latch (TABLAT) is an 8-bit register mapped
into the SFR space. The Table Latch is used to hold
8-bit data during data transfers between program
memory and data RAM.
5.2.3
The Table Pointer (TBLPTR) addresses a byte within
the program memory. The TBLPTR is comprised of
three SFR registers: Table Pointer Upper Byte, Table
Pointer High Byte and Table Pointer Low Byte
(TBLPTRU:TBLPTRH:TBLPTRL). These three regis-
ters join to form a 22-bit wide pointer. The low order 21
bits allow the device to address up to 2 Mbytes of pro-
gram memory space. The 22nd bit allows access to the
Device ID, the User ID and the Configuration bits.
The table pointer, TBLPTR, is used by the TBLRD and
TBLWT instructions. These instructions can update the
TBLPTR in one of four ways based on the table opera-
tion. These operations are shown in Table 5-1. These
operations on the TBLPTR only affect the low order
21 bits.
TABLE 5-1:
FIGURE 5-3:
DS39564C-page 58
TBLRD*+
TBLWT*+
TBLRD*-
TBLWT*-
TBLRD+*
TBLWT+*
Example
TBLRD*
TBLWT*
21
TABLAT - TABLE LATCH REGISTER
TBLPTR - TABLE POINTER
REGISTER
TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS
TBLPTRU
TABLE POINTER BOUNDARIES BASED ON OPERATION
16
ERASE - TBLPTR<21:6>
15
TBLPTR is incremented before the read/write
TBLPTR is decremented after the read/write
TBLPTR is incremented after the read/write
WRITE - TBLPTR<21:3>
TBLPTRH
READ - TBLPTR<21:0>
Operation on Table Pointer
TBLPTR is not modified
5.2.4
TBLPTR is used in reads, writes, and erases of the
FLASH program memory.
When a TBLRD is executed, all 22 bits of the Table
Pointer determine which byte is read from program
memory into TABLAT.
When a TBLWT is executed, the three LSbs of the Table
Pointer (TBLPTR<2:0>) determine which of the eight
program memory holding registers is written to. When
the timed write to program memory (long write) begins,
the 19 MSbs of the Table Pointer, TBLPTR
(TBLPTR<21:3>), will determine which program mem-
ory block of 8 bytes is written to. For more detail, see
Section 5.5 (“Writing to FLASH Program Memory”).
When an erase of program memory is executed, the 16
MSbs of the Table Pointer (TBLPTR<21:6>) point to the
64-byte block that will be erased. The Least Significant
bits (TBLPTR<5:0>) are ignored.
Figure 5-3 describes the relevant boundaries of
TBLPTR
operations.
8
7
based
TABLE POINTER BOUNDARIES
on
TBLPTRL
© 2006 Microchip Technology Inc.
FLASH
program
0
memory