AT91SAM7L64-CU Atmel, AT91SAM7L64-CU Datasheet
AT91SAM7L64-CU
Specifications of AT91SAM7L64-CU
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AT91SAM7L64-CU Summary of contents
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... Internal High-speed Flash – 128 Kbytes (AT91SAM7L128), Organized in 512 Pages of 256 Bytes Single Plane – 64 Kbytes (AT91SAM7L64), Organized In 256 Pages of 256 Bytes Single Plane – Single Cycle Access MHz in Worst Case Conditions – 128-bit Read Access – Page Programming Time: 4.6 ms, Including Page Auto Erase, Full Erase Time – ...
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... Double PWM Generation, Capture/Waveform Mode, Up/Down Capability • One Four-channel 16-bit PWM Controller (PWMC) • One Two-wire Interface (TWI) – Master, Multi-Master and Slave Mode Support, All Atmel – General Call Supported in Slave Mode • One 4-channel 10-bit Analog-to-Digital Converter, Four Channels Multiplexed with Digital I/Os ® ...
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... ARM7 • AT91SAM7L128 features a 128 Kbyte high-speed Flash and a total of 6 Kbytes SRAM. • AT91SAM7L64 features a 64 Kbyte high-speed Flash and a total of 6 Kbytes SRAM. They also embed a large set of peripherals, including a Segment LCD Controller and a complete set of system functions minimizing the number of external components. ...
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Block Diagram Figure 2-1. AT91SAM7L128/64 Block Diagram TDI TDO TMS TCK JTAGSEL TST FIQ IRQ0-IRQ1 PCK0-PCK2 CLKIN PLL PLLRC XIN OSC XOUT 32k RCOSC VDDIO1 BOD POR VDDIO1 NRST NRSTB FWUP VDDIO1 DRXD DTXD SEG00-SEG39 COM0-COM9 RXD0 TXD0 SCK0 ...
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Signal Description Table 3-1. Signal Description List Signal Name Function I/O Lines (PIOC) and Voltage Regulator VDDIO1 Power Supply VDDOUT Voltage Regulator Output VDDCORE Core Power Supply VDDINLCD Charge Pump Power Supply VDD3V6 Charge Pump Output VDDLCD LCD Voltage ...
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Table 3-1. Signal Description List (Continued) Signal Name Function NRST Microcontroller Reset TST Test Mode Select NRSTB Asynchronous Master Reset DRXD Debug Receive Data DTXD Debug Transmit Data IRQ0 - IRQ1 External Interrupt Inputs FIQ Fast Interrupt Input PA0 - ...
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Table 3-1. Signal Description List (Continued) Signal Name Function TWD Two-wire Serial Data TWCK Two-wire Serial Clock AD0-AD3 Analog Inputs ADTRG ADC Trigger ADVREF ADC Reference PGMEN0- Programming Enabling PGMEN2 PGMM0- Programming Mode PGMM3 PGMD0- Programming Data PGMD15 PGMRDY Programming ...
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Package and Pinout The AT91SAM7L128/64 is available in: • 128-lead LQFP package with a 0.5 mm lead-pitch • 144-ball LFBGA package with a 0.8 mm pitch. The part is also available ...
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LQFP Package Pinout Table 4-1. Pinout for 128-lead LQFP Package 1 TST 33 2 VDDCORE 34 3 PA0 35 4 PA1 36 5 PA2 37 6 PA3 38 7 PA4 39 8 PA5 40 9 PA6 41 10 ...
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LFBGA Package Outline Figure 4-2 A detailed mechanical description is given in the Mechanical Characteristics section of the prod- uct datasheet. Figure 4-2. AT91SAM7L128/64 Preliminary 10 shows the orientation of the 144-ball LFBGA package. 144-ball LFBGA Package Outline ...
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LFBGA Pinout Table 4-2. SAM7L128/64 Pinout for 144-ball LFBGA Package Pin Signal Name Pin A1 XOUT D1 A2 XIN D2 A3 VDDCORE D3 A4 GND D4 A5 PLLRCGND D5 A6 PLLRC D6 A7 PC24/PGMD13 D7 A8 PC23//PGMD12 D8 ...
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Power Considerations 5.1 Power Supplies The AT91SAM7L128/64 has six types of power supply pins and integrates a voltage regulator, allowing the device to be supplied with only one voltage. The six power supply pin types are: • VDDOUT pin. ...
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Table 5-1 on page 13 When entering this mode, all PIO pins keep their previous states, they are reinitialized as inputs with pull-ups at wake-up. The AT91SAM7L128/64 can be awakened from this mode through the FWUP pin, an event on ...
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Wake-up Sources The wake-up events allow the device to exit from backup mode. When a wake-up event is detected, the supply controller performs a sequence which automatically reenables the voltage regulator and the backup SRAM power supply ...
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Figure 5-2. 5.5 Voltage Regulator The AT91SAM7L128/64 embeds a voltage regulator that is managed by the supply controller. This internal regulator is only intended to supply the internal core of AT91SAM7L128/64. It fea- tures three different operating modes: • In ...
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Adequate input supply decoupling is mandatory for VDDIO1 in order to improve startup stability and reduce source voltage drop. The input decoupling capacitor should be placed close to the chip. For example, two capacitors can be used in parallel, 100 ...
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Figure 5-4. If the charge pump is not needed, the user can apply an external voltage. See Figure 5-5. Please note that in this topology, switching time enhancement buffers are not available. (Refer Section 10.13 ”Segment LCD 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary ...
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Typical Powering Schematics The AT91SAM7L128/64 supports a 1.8V-3.6V single supply mode. The internal regulator input connected to the source and its output feeds VDDCORE. ics to be used. Figure 5-6. AT91SAM7L128/64 Preliminary 18 3.3V System Single Power Supply Schematic ...
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I/O Line Considerations 6.1 JTAG Port Pins TMS, TDI and TCK are schmitt trigger inputs. TMS, TDI and TCK do not integrate a pull-up resistor. TDO is an output, driven VDDIO, and has no pull-up resistor. ...
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PIO Controller Lines All the I/O lines; PA0 to PA25, PB0 to PB23, PC0 to PC29 integrate a programmable pull-up resistor. Programming of this pull-up resistor is performed independently for each I/O line through the PIO controllers. All I/Os ...
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Processor and Architecture 7.1 ARM7TDMI Processor • RISC processor based on ARMv4T Von Neumann Architecture – Runs MHz, providing 0.9 MIPS/MHz • Two instruction sets – ARM – Thumb high code density 16-bit instruction set ...
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Embedded Flash interface three programmable wait states – Prefetch buffer, buffering and anticipating the 16-bit requests, reducing the required – Key-protected program, erase and lock/unlock sequencer – Single command for erasing, programming and locking operations – Interrupt ...
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... Protection Mode to secure contents of the Flash • 64 Kbytes of Flash Memory (AT91SAM7L64) – Single plane – One bank of 256 pages of 256 bytes – Fast access time, 15 MHz single-cycle access in Worst Case conditions – ...
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Figure 8-1. Memory Mapping Address Memory Space 0x0000 0000 Internal Memories 256 MBytes 0x0FFF FFFF 0x1000 0000 Undefined 14 x 256 MBytes (Abort) 3,584 MBytes 0xEFFF FFFF 0xF000 0000 Internal Peripherals 256M Bytes 0xFFFF FFFF AT91SAM7L128/64 Preliminary 24 Internal Memory ...
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... Internal Flash • The AT91SAM7L128 features one bank of 128 Kbytes of Flash. • The AT91SAM7L64 features one bank of 64 Kbytes of Flash. At any time, the Flash is mapped to address 0x0010 0000. A general purpose NVM (GPNVM1) bit is used to boot either on the ROM (default) or from the Flash. This GPNVM1 bit can be cleared or set respectively through the commands “ ...
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... Flash Overview • The Flash of the AT91SAM7L128 is organized in 512 pages (single plane) of 256 bytes. • The Flash of the AT91SAM7L64 is organized in 256 pages (single plane) of 256 bytes. The Flash contains a 128-byte write buffer, accessible through a 32-bit interface. 8.1.2.2 Flash Power Supply The Flash is supplied by VDDCORE through a power switch controlled by the Supply Controller ...
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... Each lock region has a size of 8 Kbytes. The AT91SAM7L64 Embedded Flash Controller manages 8 lock bits to protect 8 regions of the flash against inadvertent flash erasing or programming commands. The AT91SAM7L64 con- tains 8 lock regions and each lock region contains 32 pages of 256 bytes. Each lock region has a size of 8 Kbytes locked-region’ ...
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... TST and CLKIN are tied high while FWUP is tied low. • The Flash of the AT91SAM7L128 is organized in 512 pages of 256 bytes (single plane). • The Flash of the AT91SAM7L64 is organized in 256 pages of 256 bytes (single plane). The Flash contains a 128-byte write buffer, accessible through a 32-bit interface. ...
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System Controller The System Controller manages all vital blocks of the microcontroller, interrupts, clocks, power, time, debug and reset. The System Controller Block Diagram is shown in 9.1 System Controller Mapping The System Controller peripherals are all mapped to ...
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Figure 9-1. System Controller Block Diagram FWUP NRSTB Zero-Power Power-on Reset Brownout Detector WKUP0 - WKUP15 SLCK XIN Xtal 32 kHz Oscillator XOUT Embedded 32 kHz RC Oscillator Backup Power Supply core_nreset NRST FSTT0 - FSTT15 Embedded 2 MHz RC ...
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Supply Controller (SUPC) The Supply Controller controls the power supplies of each section of the product: • the processor and the peripherals • the Flash memory • the backup SRAM • the LCD controller, the charge pump and the ...
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BOD current consumption is 25 µA, typically. To decrease current consumption, the software can disable the brownout detector, especially in low-power mode. The software can also configure the BOD in “switched” mode. In this mode, an internal state machine switches ...
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Figure 9-2. 9.5 Power Management Controller The Power Management Controller uses the clock generator outputs to provide: • The Processor Clock PCK • The Master Clock MCK • All the peripheral clocks, independently controllable • Three programmable clock outputs PCKx ...
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Figure 9-3. 9.6 Advanced Interrupt Controller • Controls the interrupt lines (nIRQ and nFIQ ARM Processor • Individually maskable and vectored interrupt sources – Source 0 is reserved for the Fast Interrupt Input (FIQ) – Source 1 is ...
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... Chip ID Registers – Identification of the device revision, sizes of the embedded memories, set of – Chip ID is 0x2733 0740 (VERSION 0) for AT91SAM7L128 – Chip ID is 0x2733 0540 (VERSION 0) for AT91SAM7L64 9.8 Period Interval Timer • 20-bit programmable counter plus 12-bit interval counter 9 ...
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Peripherals 10.1 User Interface The User Peripherals are mapped in the 256 MBytes of the address space between 0xF000 0000 and 0xFFFF EFFF. Each peripheral is allocated 16 Kbytes of address space. A complete memory map is presented in ...
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Peripheral Multiplexing on PIO Lines The AT91SAM7L128/64 features three PIO controllers, PIOA, PIOB and PIOC, that multiplex the I/O lines of the peripheral set. PIO Controller A, B and C control respectively 26, 24 and 30 lines. Each line ...
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PIO Controller A Multiplexing Table 10-2. Multiplexing on PIO Controller A PIO Controller A I/O Line Peripheral A PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 ...
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PIO Controller B Multiplexing Table 10-3. Multiplexing on PIO Controller B I/O Line Peripheral A PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 NPCS3 PB13 NPCS2 PB14 NPCS1 PB15 RTS1 PB16 RTS0 PB17 DTR1 ...
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PIO Controller C Multiplexing Table 10-4. Multiplexing on PIO Controller C I/O Line Peripheral A PC0 CTS1 PC1 DCD1 PC2 DTR1 PC3 DSR1 PC4 RI1 PC5 IRQ1 PC6 NPCS1 PC7 PWM0 PC8 PWM1 PC9 PWM2 PC10 TWD PC11 TWCK ...
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... Maximum frequency Master Clock 10.8 Two Wire Interface • Master, Multi-Master and Slave Mode Operation • Compatibility with Atmel two-wire interface, serial memory and I • One, two or three bytes for slave address • Sequential read/write operations • Bit Rate 400 kbit/s • ...
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Multi-drop Mode with address generation and detection – Optional Manchester Encoding • RS485 with driver control signal • ISO7816 Protocols for interfacing with smart cards – NACK handling, error counter with repetition ...
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Independent channel programming – Independent enable/disable commands – Independent clock selection – Independent period and duty cycle, with double buffering – Programmable selection of the output waveform polarity – Programmable center or left aligned output waveform 10.12 Analog-to-Digital Converter ...
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AT91SAM7L128/64 Preliminary 44 6257A–ATARM–20-Feb-08 ...
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ARM7TDMI Processor Overview 11.1 Overview The ARM7TDMI core executes both the 32-bit ARM and 16-bit Thumb instruction sets, allowing the user to trade off between high performance and high code density.The ARM7TDMI proces- sor implements Von Neuman architecture, using ...
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ARM7TDMI Processor For further details on ARM7TDMI, refer to the following ARM documents: ARM Architecture Reference Manual (DDI 0100E) ARM7TDMI Technical Reference Manual (DDI 0210B) 11.2.1 Instruction Type Instructions are either 32 bits long (in ARM state ...
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Table 11-1. User and System Mode R10 R11 R12 R13 R14 PC CPSR Registers are unbanked registers. This means that each of them refers to the same ...
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A seventh processing mode, System Mode, does not have any banked registers. It uses the User Mode registers. System Mode runs tasks that require a privileged processor mode and allows them to invoke all classes of exceptions. 11.2.4.2 Status Registers ...
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Table 11-2 Table 11-2. Mnemonic MOV ADD SUB RSB CMP TST AND EOR MUL SMULL SMLAL MSR B BX LDR LDRSH LDRSB LDRH LDRB LDRBT LDRT LDM SWP MCR LDC 11.2.6 Thumb Instruction Set Overview The Thumb instruction set is ...
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Program Counter (ARM Register 15), the Link Register (ARM Register 14) and the Stack Pointer (ARM Register 13). Further instructions allow limited access to the ARM registers 8 to 15. Table 11-3 Table 11-3. Mnemonic MOV ADD ...
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Debug and Test Features 12.1 Overview The AT91SAM7L Series Microcontrollers feature a number of complementary debug and test capabilities. A common JTAG/ICE (Embedded ICE) port is used for standard debugging func- tions, such as downloading code and single-stepping through ...
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Application Examples 12.3.1 Debug Environment Figure 12-2 standard debugging functions, such as downloading code and single-stepping through the program. Figure 12-2. Application Debug Environment Example AT91SAM7L128/64 Preliminary 52 shows a complete debug environment example. The ICE/JTAG interface is used ...
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Test Environment Figure 12-3 tester. In this example, the “board in test” is designed using a number of JTAG-compliant devices. These devices can be connected to form a single scan chain. Figure 12-3. Application Test Environment Example 12.4 Debug ...
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... Debug Unit allows blockage of access to the system through the ICE interface. A specific register, the Debug Unit Chip ID Register, gives information about the product version and its internal configuration. Table 12-2. Chip Name AT91SAM7L64 AT91SAM7L128 For further details on the Debug Unit, see the Debug Unit section. 12.5.4 IEEE 1149.1 JTAG Boundary Scan IEEE 1149 ...
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IEEE 1149.1 JTAG Boundary Scan is enabled when TST, JTAGSEL are high and CLKIN, FWUP and RNRSTB are tied low. VDDCORE must be externally supplied between 1.8V and 1.95V. The SAMPLE, EXTEST and BYPASS functions are implemented. In ICE debug ...
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... PART NUMBER 7 6 • VERSION[31:28]: Product Version Number Set to 0x0. • PART NUMBER[27:12]: Product Part Number Chip Name AT91SAM7L64 AT91SAM7L128 • MANUFACTURER IDENTITY[11:1] Set to 0x01F. • Bit[0] Required by IEEE Std. 1149.1. Set to 0x1. Chip Name AT91SAM7L64 AT91SAM7L128 AT91SAM7L128/64 Preliminary PART NUMBER ...
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Reset Controller (RSTC) 13.1 Overview The Reset Controller (RSTC), based on a zero-power power-on reset cell, handles all the resets of the system without any external components. It reports which reset occurred last. The Reset Controller also drives independently ...
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The Reset Controller Mode Register (RSTC_MR), allowing the configuration of the Reset Con- troller, is powered with VDDIO1, so that its configuration is saved as long as VDDIO1 is on. 13.3.2 NRST Manager The NRST Manager samples the NRST input ...
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Please note that the NRST output is in high impedance state when the chip is in OFF mode. 13.3.3 Brownout Manager The Brownout manager is embedded within the Supply Controller, please refer to the Supply Controller section for a detailed ...
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Backup Reset A Backup reset occurs when the chip returns from Backup mode. The core_backup_reset signal is asserted by the Supply Controller when a Backup reset occurs. The field RSTTYP in RSTC_SR is updated to report a Backup Reset. ...
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Software Reset The Reset Controller offers several commands used to assert the different reset signals. These commands are performed by writing the Control Register (RSTC_CR) with the following bits at 1: • PROCRST: Writing PROCRST at 1 resets the ...
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Figure 13-5. Software Reset SLCK MCK Freq. Write RSTC_CR proc_nreset if PROCRST=1 RSTTYP periph_nreset if PERRST=1 NRST (nrst_out) if EXTRST=1 SRCMP in RSTC_SR 13.3.4.5 Watchdog Reset The Watchdog Reset is entered when a watchdog fault occurs. This state lasts 3 ...
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Figure 13-6. Watchdog Reset SLCK MCK wd_fault proc_nreset RSTTYP periph_nreset Only if WDRPROC = 0 NRST (nrst_out) 13.3.5 Reset State Priorities The Reset State Manager manages the following priorities between the different reset sources, given in descending order: • General ...
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SRCMP bit: This field indicates that a Software Reset Command is in progress and that no further software reset should be performed until the end of the current one. This bit is automatically cleared at the end of the ...
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Reset Controller (RSTC) User Interface Table 13-1. Register Mapping Offset Register 0x00 Control Register 0x04 Status Register 0x08 Mode Register 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary Name Access RSTC_CR Write-only RSTC_SR Read-only RSTC_MR Read-write Reset - 0x0000_0000 0x0000_0000 65 ...
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Reset Controller Control Register Name: RSTC_CR Access Type: Write-only – – – – – – • PROCRST: Processor Reset effect KEY is correct, resets the ...
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Reset Controller Status Register Name: RSTC_SR Access Type: Read-only 31 30 – – – – – – – – • URSTS: User Reset Status high-to-low edge on NRST happened since ...
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Reset Controller Mode Register Name: RSTC_MR Access Type: Read-write – – – – – – • URSTEN: User Reset Enable 0 = The detection of a low level on the pin ...
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Real-time Clock (RTC) 14.1 Overview The Real-time Clock (RTC) peripheral is designed for very low power consumption. It combines a complete time-of-day clock with alarm and a two-hundred-year Gregorian calen- dar, complemented by a programmable periodic interrupt. The alarm ...
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... After hardware reset, the calendar is initialized to Thursday, January 1, 1998. 14.4.1 Reference Clock The reference clock is Slow Clock (SLCK). It can be driven by the Atmel cell OSC55 or OSC56 (or an equivalent cell) and an external 32.768 kHz crystal. During low power modes of the processor (idle mode), the oscillator runs and power consump- tion is critical ...
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Century (check range 19 - 20) 2. Year (BCD entry check) 3. Date (check range 01 - 31) 4. Month (check BCD range 01 - 12, check validity regarding “date”) 5. ...
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Figure 14-2. Update Sequence Prepare TIme or Calendar Fields Set UPDTIM and/or UPDCAL Clear ACKUPD bit in RTC_SCCR Update Time andor Calendar values in Clear UPDTIM and/or UPDCAL bit in AT91SAM7L128/64 Preliminary 72 Begin bit(s) in RTC_CR Read RTC_SR No ...
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Real-time Clock (RTC) User Interface Table 14-1. Register Mapping Offset Register 0x00 Control Register 0x04 Mode Register 0x08 Time Register 0x0C Calendar Register 0x10 Time Alarm Register 0x14 Calendar Alarm Register 0x18 Status Register 0x1C Status Clear Command Register ...
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RTC Control Register Name: RTC_CR Access Type: Read-write 31 30 – – – – – – – – • UPDTIM: Update Request Time Register effect Stops the RTC ...
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RTC Mode Register Name: RTC_MR Access Type: Read-write 31 30 – – – – – – – – • HRMOD: 12-/24-hour Mode 0 = 24-hour mode is selected 12-hour mode is ...
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RTC Time Register Name: RTC_TIMR Access Type: Read-write 31 30 – – – AMPM 15 14 – – • SEC: Current Second The range that can be set (BCD). The lowest ...
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RTC Calendar Register Name: RTC_CALR Access Type: Read-write 31 30 – – DAY – • CENT: Current Century The range that can be set (BCD). The lowest four bits ...
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RTC Time Alarm Register Name: RTC_TIMALR Access Type: Read-write 31 30 – – HOUREN AMPM 15 14 MINEN 7 6 SECEN • SEC: Second Alarm This field is the alarm field corresponding to the BCD-coded second counter. ...
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RTC Calendar Alarm Register Name: RTC_CALALR Access Type: Read-write 31 30 DATEEN – MTHEN – – – – – • MONTH: Month Alarm This field is the alarm field corresponding to the BCD-coded ...
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RTC Status Register Name: RTC_SR Access Type: Read-only 31 30 – – – – – – – – • ACKUPD: Acknowledge for Update 0 = Time and calendar registers cannot be updated. 1 ...
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RTC Status Clear Command Register Name: RTC_SCCR Access Type: Write-only 31 30 – – – – – – – – • ACKCLR: Acknowledge Clear effect Clears corresponding status ...
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RTC Interrupt Enable Register Name: RTC_IER Access Type: Write-only 31 30 – – – – – – – – • ACKEN: Acknowledge Update Interrupt Enable effect The acknowledge ...
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RTC Interrupt Disable Register Name: RTC_IDR Access Type: Write-only 31 30 – – – – – – – – • ACKDIS: Acknowledge Update Interrupt Disable effect The acknowledge ...
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RTC Interrupt Mask Register Name: RTC_IMR Access Type:Read-only 31 30 – – – – – – – – • ACK: Acknowledge Update Interrupt Mask 0 = The acknowledge for update interrupt is disabled. ...
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RTC Valid Entry Register Name: RTC_VER Access Type: Read-only 31 30 – – – – – – – – • NVTIM: Non-valid Time invalid data has been detected in RTC_TIMR ...
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AT91SAM7L128/64 Preliminary 86 6257A–ATARM–20-Feb-08 ...
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Periodic Interval Timer (PIT) 15.1 Overview The Periodic Interval Timer (PIT) provides the operating system’s scheduler interrupt designed to offer maximum accuracy and efficient management, even for systems with long response time. 15.2 Block Diagram Figure 15-1. ...
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Functional Description The Periodic Interval Timer aims at providing periodic interrupts for use by operating systems. The PIT provides a programmable overflow counter and a reset-on-read feature built around two counters: a 20-bit CPIV counter and a ...
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Figure 15-2. Enabling/Disabling PIT with PITEN 15 MCK Prescaler 0 PITEN CPIV 0 PICNT PITS (PIT_SR) APB Interface 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary MCK 1 PIV - 1 PIV 1 0 read PIT_PIVR APB cycle APB cycle restarts MCK Prescaler 0 0 ...
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Periodic Interval Timer (PIT) User Interface Table 15-1. Register Mapping Offset Register 0x00 Mode Register 0x04 Status Register 0x08 Periodic Interval Value Register 0x0C Periodic Interval Image Register AT91SAM7L128/64 Preliminary 90 Name Access PIT_MR Read-write PIT_SR Read-only PIT_PIVR Read-only ...
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Periodic Interval Timer Mode Register Register Name: PIT_MR Access Type: Read-write 31 30 – – – – • PIV: Periodic Interval Value Defines the value compared with the primary 20-bit counter of the ...
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Periodic Interval Timer Status Register Register Name: PIT_SR Access Type: Read-only 31 30 – – – – – – – – • PITS: Periodic Interval Timer Status 0 = The Periodic Interval timer ...
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Periodic Interval Timer Value Register Register Name: PIT_PIVR Access Type: Read-only PICNT Reading this register clears PITS in PIT_SR. • CPIV: Current Periodic Interval Value Returns the current value of the ...
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Periodic Interval Timer Image Register Register Name: PIT_PIIR Access Type: Read-only PICNT • CPIV: Current Periodic Interval Value Returns the current value of the periodic interval timer. • PICNT: Periodic Interval ...
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Watchdog Timer (WDT) 16.1 Overview The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. It features a 12-bit down counter that allows a watchdog period seconds ...
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Functional Description The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock supplied with VDDCORE. It restarts with initial values on processor reset. The Watchdog is built around a ...
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Figure 16-2. Watchdog Behavior FFF Normal behavior WDV Forbidden Window WDD Permitted Window 0 Watchdog Fault 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary Watchdog Error WDT_CR = WDRSTT Watchdog Underflow if WDRSTEN WDRSTEN ...
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Watchdog Timer (WDT) User Interface Table 16-1. Register Mapping Offset Register 0x00 Control Register 0x04 Mode Register 0x08 Status Register AT91SAM7L128/64 Preliminary 98 Name Access WDT_CR Write-only WDT_MR Read-write Once WDT_SR Read-only Reset - 0x3FFF_2FFF 0x0000_0000 6257A–ATARM–20-Feb-08 ...
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Watchdog Timer Control Register Register Name: WDT_CR Access Type: Write-only – – – – – – • WDRSTT: Watchdog Restart 0: No effect. 1: Restarts the Watchdog. • KEY: Password Should ...
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Watchdog Timer Mode Register Register Name: WDT_MR Access Type: Read-write Once 31 30 – – WDIDLEHLT WDDIS WDRPROC WDRSTEN 7 6 • WDV: Watchdog Counter Value Defines the value loaded in the 12-bit Watchdog Counter. ...
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WDDIS: Watchdog Disable 0: Enables the Watchdog Timer. 1: Disables the Watchdog Timer. 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary 101 ...
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Watchdog Timer Status Register Register Name: WDT_SR Access Type: Read-only 31 30 – – – – – – – – • WDUNF: Watchdog Underflow 0: No Watchdog underflow occurred since the last read ...
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Supply Controller (SUPC) 17.1 Overview The Supply Controller (SUPC) controls the supply voltages of the system typical applica- tion, the Supply Controller allows supply of the device directly from a double NiMH or NiCd battery or from ...
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Block Diagram Figure 17-1. Supply Controller Block Diagram Brownout Detector Zero-power Power-on Reset Embedded 32 kHz RC Oscillator XIN Xtal 32 kHz Oscillator 0 ...
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Supply Controller Functional Description 17.3.1 Supply Controller Overview The Supply Controller controls the power supplies of each section of the product: • The Backup, including the Supply Controller, a part of the Reset Controller and the Slow Clock switcher ...
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OSCBYPASS bit of the Supply Controller Mode Register (SUPC_MR) needs to be set at 1. 17.3.3 Brownout Detector The Supply Controller embeds a Brownout Detector. The Brownout Detector can be used to prevent the processor from falling ...
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Reading FWUPS to 0 means SUPC_SR has already been read since the power up of the backup power supply and thus not necessary to initialize the Supply Controller. Figure 17-2. Raising the Backup Power Supply FWUP Backup Power ...
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Figure 17-3. NRSTB Reset when FWUP = 0 NRSTB FWUP RC Oscillator output supply_on sram_on vr_standby vr_ok vddcore_nreset Figure 17-4. NRSTB Reset when FWUP = 1 and NRSTB is Released Before FWUP = 0 NRSTB FWUP RC Oscillator output supply_on ...
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Figure 17-5. NRSTB Reset when FWUP = 1 and NRSTB is Released After FWUP = 0 NRSTB FWUP RC Oscillator output supply_on sram_on vr_standby vr_ok core_nreset 17.3.5 Core Reset The Supply Controller manages the vddcore_nreset signal to the Reset Controller, ...
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Until vr_ok is deactivated, the vddcore_nreset signal remains active. 17.3.6 Power Supply Control 17.3.6.1 Controlling the Backup Power Supply The backup power supply can be controlled by the main power switch. This main power switch can only be enabled by ...
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Figure 17-6. Shutdown of the Backup Power Supply After Writing SHDW at 1 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary slow_clock write_shdw write_shdw_slck vddcore_nreset vr_standby flash_off flash_poe VDDCORE sram_on lcd_nreset lcd_pump_on rt_nreset rt_on supply_on VDDBU 111 ...
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Figure 17-7. Shutdown of the Backup Power Supply After Writing SHDWEOF at 1 write_shdweof_slck 17.3.6.2 Controlling the Voltage Regulator The Supply Controller can be used to control the embedded 1.8V voltage regulator. The VRVDD field in the Supply Controller Mode ...
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Once the vddcore_nreset signal is asserted, the processor and the peripherals are stopped 1 slow clock cycle before the core power supply becomes off. The loss of voltage regulation while the core power supply is ...
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The status of the LCD Controller Reset can be seen through the LCDS field in the status regis- ter, SUPC_ SR. • If LCDMODE is written to 0x2 while 0x0 or 0x1, after the write resynchronization time ...
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The Flash Memory is automatically switched on when the core power supply is enabled at start up. The status of the Flash Memory, i.e., ready to use, or not ready, can be seen through the FLASHS field in the status ...
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Figure 17-8. Wake Up Sources BODEN brown_out RTCEN rtc_alarm Falling/Rising Edge FWUP Detector WKUPT0 Falling/Rising Edge WKUP0 Detector WKUPT1 Falling/Rising WKUP1 Edge Detector WKUPT15 WKUPEN15 Falling/Rising WKUP15 Edge Detector 17.3.7.1 Force Wake Up The Force Wake Up pin, FWUP is ...
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All the resulting signals are wired-ORed to trigger a debounce counter, which can be pro- grammed with the WKUPDBC field in the Supply Controller Wake Up Mode Register, SUPC_WUMR. The WKUPDBC field can select a debouncing period of 3, 32, ...
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Supply Controller (SUPC) User Interface The User Interface of the Supply Controller is part of the System Controller User Interface. 17.4.1 System Controller (SYSC) User Interface Table 17-1. System Controller Registers Offset System Controller Peripheral 0x00-0x0c Reset Controller 0x10-0x2C ...
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Supply Controller Control Register Register Name: SUPC_CR Access Type: Write-only – – – – – – • SHDW: Shut Down Command effect KEY is correct, ...
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Supply Controller Brownout Mode Register Register Name: SUPC_BOMR Access Type: Read-write 31 30 – – – – – – – – • BODTH: Brownout Threshold BODTH 0x0 0x1 0x2 0x3 0x4 0x5 0x6 ...
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BODRSTEN: Brownout Reset Enable 0 = The core reset signal, vddcore_nreset is not affected when a brownout occurs The core reset signal, vddcore_nreset is asserted when a brownout occurs. 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary 121 ...
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Supply Controller Mode Register Register Name: SUPC_MR Access Type: Read-write – – – – – – • LCDOUT: LCD Charge Pump Output Voltage Selection LCDOUT LCD Charge Pump Output Voltage 0x0 ...
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LCDMODE LCD Controller Power Supply At the End of Frame from the LCD Controller, the internal supply source and the external supply source are 0x1 both deselected and the on-chip charge pump is turned off. 0x2 The external supply source ...
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Supply Controller Wake Up Mode Register Register Name: SUPC_WUMR Access Type: Read-write 31 30 – – – – – WKUPDBC 7 6 – – • FWUPEN: Force Wake Up Enable 0 = The Force Wake ...
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WUPDBC Wake Up Inputs Debouncer 0x3 An enabled wake-up input shall be active for at least 512 SLCK periods 0x4 An enabled wake-up input shall be active for at least 4,096 SLCK periods 0x5 An enabled wake-up input shall be ...
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System Controller Wake Up Inputs Register Register Name: SDC_WUIR Access Type: Read-write 31 30 WKUPT15 WKUPT14 WKUPT13 23 22 WKUPT7 WKUPT6 WKUPT5 15 14 WKUPEN15 WKUPEN14 WKUPEN13 7 6 WKUPEN7 WKUPEN6 WKUPEN5 • WKUPEN0 - WKUPEN15: Wake Up Input ...
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Supply Controller Status Register Register Name: SUPC_SR Access Type: Read-write 31 30 WKUPIS15 WKUPIS14 WKUPIS13 23 22 WKUPIS7 WKUPIS6 15 14 – – OSCSEL BROWNOUT • FWUPS: FWUP Wake Up Status wake up due ...
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OSCSEL: 32-kHz Oscillator Selection Status 0 = The slow clock, SLCK is generated by the embedded 32-kHz RC oscillator The slow clock, SLCK is generated by the 32-kHz crystal oscillator. • LCDS: LCD Status 0 = The ...
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Supply Controller Flash Wake Up Timer Register Register Name: SUPC_FWUTR Access Type: Read-write 31 30 – – – – – – • FWUT: Flash Wake Up Timer Before waking up the Flash Memory ...
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AT91SAM7L128/64 Preliminary 130 6257A–ATARM–20-Feb-08 ...
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Memory Controller (MC) 18.1 Overview The Memory Controller (MC) manages the ASB bus and controls accesses requested by the masters, typically the ARM7TDMI processor and the Peripheral DMA Controller. It features a bus arbiter, an address decoder, an abort ...
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Functional Description The Memory Controller handles the internal ASB bus and arbitrates the accesses three masters made up of: • A bus arbiter • An address decoder • An abort status • A misalignment ...
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Internal Memory Mapping Within the Internal Memory address space, the Address Decoder of the Memory Controller decodes eight more address bits to allocate 1-Mbyte address spaces for the embedded memories. The allocated memories are accessed all along the 1-Mbyte ...
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Figure 18-4. Internal Memory Mapping with GPNVM Bit 18.3.3 Remap Command After execution, the Remap Command causes the Internal SRAM to be accessed through the Internal Memory Area 0. As the ARM vectors (Reset, Abort, Data Abort, ...
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UNDADD misaligned address (bit MISADD) • the source of the access leading to the last abort (bits MST_EMAC, MST_PDC and MST_ARM) • whether or not an ...
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Memory Controller (MC) User Interface Base Address: 0xFFFFFF00 Table 18-1. Memory Controller (MC) Register Mapping Offset Register 0x00 MC Remap Control Register 0x04 MC Abort Status Register 0x08 MC Abort Address Status Register 0x10-0x5C Reserved 0x60 EFC0 Configuration Registers ...
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MC Remap Control Register Register Name: MC_RCR Access Type: Write-only Offset: 0x0 31 30 – – – – – – – – • RCB: Remap Command Bit 0: No effect. 1: This Command ...
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MC Abort Status Register Register Name: MC_ASR Access Type: Read-only Reset Value: 0x0 Offset: 0x04 31 30 – – – – – – – – • UNDADD: Undefined Address Abort Status 0: The ...
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MST_PDC: PDC Abort Source 0: The last aborted access was not due to the PDC. 1: The last aborted access was due to the PDC. • MST_ARM: ARM Abort Source 0: The last aborted access was not due to ...
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MC Abort Address Status Register Register Name: MC_AASR Access Type: Read-only Reset Value: 0x0 Offset: 0x08 • ABTADD: Abort Address This field contains the address of the last aborted access. AT91SAM7L128/64 ...
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Enhanced Embedded Flash Controller (EEFC) 19.1 Overview The Enhanced Embedded Flash Controller (EEFC) ensures the interface of the Flash block with the 32-bit internal bus. Its 128-bit wide memory interface increases performance. It also man- ages the programming, erasing, ...
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Figure 19-1. Embedded Flash Organization Start Address + Flash size -1 AT91SAM7L128/64 Preliminary 142 Memory Plane Page 0 Start Address Page (m-1) Page (n*m-1) Lock Region 0 Lock Bit 0 Lock Region 1 Lock Bit 1 Lock Region (n-1) Lock ...
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Read Operations An optimized controller manages embedded Flash reads, thus increasing performance when the processor is running in ARM and Thumb mode by means of the 128-bit wide memory interface. The Flash memory is accessible through 8-, 16- and ...
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Figure 19-3. Code Read Optimization in ARM Mode for FWS = 3 Master Clock ARM Request (32-bit) @Byte 0 Flash Access Bytes 0-15 Buffer 0 (128bits) XXX Buffer 1 (128bits) Data To ARM XXX Note: When FWS is included between ...
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Data Read Optimization The organization of the Flash in 128 bits is associated with two 128-bit prefetch buffers and one 128-bit data read buffer, thus providing maximum system performance. This buffer is added in order to start access at ...
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Table 19-1. Command Set GPNVM Bit Clear GPNVM Bit Get GPNVM Bit In order to perform one of these commands, the Flash Command Register (MC_FCR) has to be written with the correct command using the field FCMD. As soon as ...
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Figure 19-6. Command State Chart 19.3.3.1 Getting Embedded Flash Descriptor This command allows the system to learn about the Flash organization. The system can take full advantage of this information. For instance, a device could be replaced by one with ...
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Table 19-2. Flash Descriptor Definition Symbol FL_ID FL_SIZE FL_PAGE_SIZE FL_NB_PLANE FL_PLANE[0] ... FL_PLANE[FL_NB_PLANE-1] FL_NB_LOCK FL_LOCK[0] ... 19.3.3.2 Write Commands Several commands can be used to program the Flash. Flash technology requires that an erase is done before programming. The full ...
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Lock Error: the page to be programmed belongs to a locked region. A command must be previously run to unlock the corresponding region. By using the WP command, a page can be programmed in several steps if it ...
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When the locking completes, the bit FRDY in the Flash Programming Status Register (MC_FSR) rises interrupt has been enabled by setting the bit FRDY in MC_FMR, the interrupt line of the Memory Controller is activated. • If ...
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When the GPVNM bit is set, the bit FRDY in the Flash Programming Status Register (MC_FSR) rises interrupt was enabled by setting the bit FRDY in MC_FMR, the interrupt line of the Memory Controller is activated. • ...
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Enhanced Embedded Flash Controller (EEFC) User Interface The User Interface of the Enhanced Embedded Flash Controller (EEFC) is integrated within the Memory Controller with base address 0xFFFF FF60 . Table 19-3. Register Mapping Offset Register MC 0x00 Flash Mode ...
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MC Flash Mode Register Register Name: MC_FMR Access Type: Read-write Offset: 0x60 31 30 – – – – – – – • FRDY: Ready Interrupt Enable 0: Flash Ready does not generate an ...
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MC Flash Command Register Register Name: MC_FCR Access Type: Write-only Offset: 0x64 • FCMD: Flash Command This field defines the flash commands. Refer to • FARG: Flash Command Argument For erase ...
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MC Flash Status Register Register Name: MC_FSR Access Type: Read-only Offset: 0x68 31 30 – – – – – – – – • FRDY: Flash Ready Status 0: The Enhanced Embedded Flash Controller ...
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MC Flash Result Register Register Name: MC_FRR Access Type: Read-only Offset: 0x6C • FVALUE: Flash Result Value The result of a Flash command is returned in this register. If the size ...
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Fast Flash Programming Interface (FFPI) 20.1 Overview The Fast Flash Programming Interface provides two solutions - parallel or serial - for high-vol- ume programming using a standard gang programmer. The parallel interface is fully handshaked and the device is ...
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Table 20-1. Signal Description List Signal Name Function VDDIO1 I/O Lines Power Supply VDDIO2 I/O Lines Power Supply VDDCORE Core Power Supply VDDOUT Voltage Regulator Output VDDINLCD Charge pump input VDD3V6 Charge pump output VDDLCD LCD voltage input GND Ground ...
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Figure 20-2. The Charge Pump and the LCD Regulator are Not Used 20.2.2 Signal Names Depending on the MODE settings, DATA is latched in different internal registers. Table 20-2. MODE[3:0] 0000 0001 0010 0101 Default When MODE is equal to ...
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Table 20-3. DATA[15:0] 0x0044 0x0025 0x0054 0x0035 0x001F 0x001E 20.2.3 Entering Programming Mode The following algorithm puts the device in Parallel Programming Mode: • Apply GND, TST, CLKIN, FWUP and the supplies as described in table 4.1. • Apply XIN ...
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Table 20-4. Write Handshake Step Programmer Action 1 Sets MODE and DATA signals 2 Clears NCMD signal 3 Waits for RDY low 4 Releases MODE and DATA signals 5 Sets NCMD signal 6 Waits for RDY high 20.2.4.2 Read Handshaking ...
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Table 20-5. Read Handshake (Continued) Step Programmer Action 9 Sets NOE signal 10 Waits for NVALID high 11 Sets DATA in output mode 12 Sets NCMD signal 13 Waits for RDY high 20.2.5 Device Operations Several commands on the Flash ...
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The Write Page command (WP) is optimized for consecutive writes. Write handshaking can be chained; an internal address buffer is automatically increased. Table 20-7. Step ... n n+1 n+2 n+3 ... The Flash command Write ...
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In the same way, the Clear Lock command (CLB) is used to clear lock bits. All the lock bits are also cleared by the EA command. Table 20-9. Step 1 2 Lock bits can be read using Get Lock Bit ...
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Table 20-13. Set Security Bit Command Step 1 2 Once the security bit is set not possible to access FFPI. The only way to erase the security bit is to erase the Flash. In order to erase the ...
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Serial Fast Flash Programming The Serial Fast Flash programming interface is based on IEEE Std. 1149.1 “Standard Test Access Port and Boundary-Scan Architecture”. Refer to this standard for an explanation of terms used in this chapter and for a ...
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Table 20-16. Signal Description List (Continued) Signal Name Function TCK JTAG TCK TDI JTAG Test Data In TDO JTAG Test Data Out TMS JTAG Test Mode Select Note: 1. See Figure 20-6 below. Figure 20-6. The Charge Pump and the ...
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Table 20-17. Reset TAP Controller and Go to Select-DR-Scan 20.3.3 Read/Write Handshake The read/write handshake is done by carrying out read/write operations on two registers of the device that are accessible through the JTAG: • Debug Comms Control Register: DCCR ...
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Bit 0 (R): Denotes whether the programmer can send data from the Debug Comms The write handshake is done by polling the Debug Comms Control Register until the R bit is cleared. Once cleared, data can be written to ...
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Table 20-19. Write Command (Continued) Read/Write Write Write Write Flash Write Page and Lock command (WPL) is equivalent to the Flash Write Command. How- ever, the lock bit is automatically set at the end of the Flash write operation. As ...
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Flash General-purpose NVM Commands General-purpose NVM bits (GP NVM) can be set with the Set GPNVM command (SGPB). Using this command, several GP NVM bits can be activated at the same time. Bit 0 of Bit Mask corre- sponds ...
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Table 20-26. Write Command Read/Write Write Write Write Write Write Write 20.3.4.8 Get Version Command The Get Version (GVE) command retrieves the version of the FFPI interface. Table 20-27. Get Version Command Read/Write Write Read AT91SAM7L128/64 Preliminary 172 DR Data ...
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AT91SAM Boot Program 21.1 Overview The Boot Program integrates different programs permitting download and/or upload into the dif- ferent memories of the product. SAM- set to 0. Once running, SAM-BA quency, then it waits for transactions on ...
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SAM-BA Boot The SAM-BA boot principle is to: – Check if the AutoBaudrate sequence has succeeded (see – Check if characters have been received on the DBGU Figure 21-2. AutoBaudrate Flow Diagram AT91SAM7L128/64 Preliminary 174 Device Setup No Character ...
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Once the communication interface is identified, the application runs in an infinite Table 21-1. Command • Write commands: Write a byte (O), a halfword ( word (W) ...
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SRAM size embedded in the product. In all cases, the size of the binary file must be lower than the SRAM size because the Xmodem protocol requires some SRAM memory to work. 21.4.2 ...
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In-Application Programming (IAP) Feature The IAP feature is a function located in ROM that can be called by any software application. When called, this function sends the desired FLASH command to the EEFC and waits for the FLASH to ...
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Hardware and Software Constraints Table 21-2. Peripheral DBGU DBGU Using a 32.768 KHz crystal is not mandatory since SAM-BA boot will automatically use the inter- nal 32Khz RC oscillator. PLL MUL parameter is automatically adapted to provide 115200 baudrate ...
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Peripheral DMA Controller (PDC) 22.1 Overview The Peripheral DMA Controller (PDC) transfers data between on-chip serial peripherals such as the UART, USART, SSC, SPI, MCI and the on- and off-chip memories. Using the Peripheral DMA Controller avoids processor intervention ...
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Functional Description 22.3.1 Configuration The PDC channels user interface enables the user to configure and control the data transfers for each channel. The user interface of a PDC channel is integrated into the user interface of the peripheral (offset ...
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If the counter is reprogrammed while the PDC is operating, the number of transfers is updated and the PDC counts transfers from the new value. Programming the Next Counter/Pointer registers chains the buffers. The counters are decre- mented after each ...
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Peripheral DMA Controller (PDC) User Interface Table 22-1. Register Mapping Offset Register 0x100 Receive Pointer Register 0x104 Receive Counter Register 0x108 Transmit Pointer Register 0x10C Transmit Counter Register 0x110 Receive Next Pointer Register 0x114 Receive Next Counter Register 0x118 ...
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PDC Receive Pointer Register Register Name: PERIPH_RPR Access Type: Read-write • RXPTR: Receive Pointer Address Address of the next receive transfer. 22.4.2 PDC Receive Counter Register Register Name: PERIPH_RCR Access Type: ...
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PDC Transmit Pointer Register Register Name: PERIPH_TPR Access Type: Read-write • TXPTR: Transmit Pointer Address Address of the transmit buffer. 22.4.4 PDC Transmit Counter Register Register Name: PERIPH_TCR Access Type: Read-write ...
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PDC Receive Next Pointer Register Register Name: PERIPH_RNPR Access Type: Read-write • RXNPTR: Receive Next Pointer Address RXNPTR is the address of the next buffer to fill with received data when ...
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PDC Transmit Next Pointer Register Register Name: PERIPH_TNPR Access Type: Read-write • TXNPTR: Transmit Next Pointer Address TXNPTR is the address of the next buffer to transmit when the current buffer ...
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PDC Transfer Control Register Register Name: PERIPH_PTCR - Access Type: Write only 31 30 – – – – – – – – • RXTEN: Receiver Transfer Enable effect ...
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PDC Transfer Status Register Register Name: PERIPH_PTSR Access Type: Read-only 31 30 – – – – – – – – • RXTEN: Receiver Transfer Enable 0 = Receiver PDC transfer requests are disabled. ...
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Advanced Interrupt Controller (AIC) 23.1 Overview The Advanced Interrupt Controller (AIC 8-level priority, individually maskable, vectored interrupt controller, providing handling thirty-two interrupt sources designed to sub- stantially reduce the software and real-time ...
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Block Diagram Figure 23-1. Block Diagram 23.3 Application Block Diagram Figure 23-2. Description of the Application Block 23.4 AIC Detailed Block Diagram Figure 23-3. AIC Detailed Block Diagram AT91SAM7L128/64 Preliminary 190 FIQ IRQ0-IRQn Embedded PeripheralEE Embedded Peripheral Embedded Peripheral ...
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I/O Line Description Table 23-1. I/O Line Description Pin Name FIQ IRQ0 - IRQn 23.6 Product Dependencies 23.6.1 I/O Lines The interrupt signals FIQ and IRQ0 to IRQn are normally multiplexed through the PIO control- lers. Depending on the ...
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Functional Description 23.7.1 Interrupt Source Control 23.7.1.1 Interrupt Source Mode The Advanced Interrupt Controller independently programs each interrupt source. The SRC- TYPE field of the corresponding AIC_SMR (Source Mode Register) selects the interrupt condition of each source. The internal ...
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Internal Interrupt Source Input Stage Figure 23-4. 23.7.1.6 External Interrupt Source Input Stage Figure 23-5. External Interrupt Source Input Stage Source i AIC_ISCR AIC_ICCR 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary Internal Interrupt Source Input Stage AIC_SMRI (SRCTYPE) Level/ Source i Edge Edge ...
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Interrupt Latencies Global interrupt latencies depend on several parameters, including: • The time the software masks the interrupts. • Occurrence, either at the processor level or at the AIC level. • The execution time of the instruction in progress ...
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Internal Interrupt Edge Triggered Source Figure 23-8. 23.7.2.4 Internal Interrupt Level Sensitive Source Figure 23-9. 23.7.3 Normal Interrupt 23.7.3.1 Priority Controller An 8-level priority controller drives the nIRQ line of the processor, depending on the interrupt conditions occurring on ...
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The nIRQ line can be asserted only if an interrupt condition occurs on an interrupt source with a higher priority interrupt condition happens (or is pending) during the interrupt treatment in progress delayed until the software ...
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It is assumed that: 1. The Advanced Interrupt Controller has been programmed, AIC_SVR registers are loaded with corresponding interrupt service routine addresses and interrupts are enabled. 2. The instruction at the ARM interrupt exception vector address is required to work ...
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Note: 23.7.4 Fast Interrupt 23.7.4.1 Fast Interrupt Source The interrupt source 0 is the only source which can raise a fast interrupt request to the processor except if fast forcing is used. The interrupt source 0 is generally connected to ...
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ARM core adjusts R14_fiq, decre- menting it by four. 2. The ARM core enters FIQ mode. 3. When the instruction loaded at address 0x1C is executed, the program counter is loaded ...
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The FIQ Vector Register (AIC_FVR) reads the contents of the Source Vector Register 0 (AIC_SVR0), whatever the source of the fast interrupt may be. The read of the FVR does not clear the Source 0 when the fast forcing feature ...