AT91SAM7A3-AU Atmel, AT91SAM7A3-AU Datasheet
AT91SAM7A3-AU
Specifications of AT91SAM7A3-AU
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AT91SAM7A3-AU Summary of contents
Page 1
... Two 32-bit Battery Backup Registers for a Total of 8 Bytes • One 8-channel 20-bit PWM Controller (PWMC) • One USB 2.0 Full Speed (12 Mbits per Second) Device Port – On-chip Transceiver, 2376-byte Configurable Integrated FIFOs ® ® Thumb Processor AT91 ARM Thumb-based Microcontrollers AT91SAM7A3 Preliminary 6042E–ATARM–14-Dec-06 ...
Page 2
... VDDANA ADC Power Supply – 3.6V VDDBU Backup Power Supply • 5V-tolerant I/Os • Fully Static Operation MHz at 1.65V and 85°C Worst Case Conditions • Available in a 100-lead LQFP Green Package AT91SAM7A3 Preliminary 2 ® Infrared Modulation/Demodulation 6042E–ATARM–14-Dec-06 ...
Page 3
... By combining a high-performance 32-bit RISC processor with a high-density 16-bit instruction set, Flash and SRAM memory, a wide range of peripherals including CAN controllers, 10-bit ADC, Timers and serial communication channels monolithic chip, the AT91SAM7A3 is ideal for many compute-intensive embedded control applications. 6042E–ATARM–14-Dec-06 AT91SAM7A3 Preliminary ™ ...
Page 4
... Block Diagram Figure 2-1. AT91SAM7A3 Block Diagram TDI TDO TMS TCK JTAGSEL System Controller TST FIQ IRQ0-IRQ3 DRXD DTXD PCK0-PCK3 PLLRC PLL XIN OSC XOUT GND VDDBU RCOSC FWKUP WKUP0 WKUP1 SHDW POR VDDBU VDD3V3 POR VDD1V8 POR NRST PIOA RXD0 ...
Page 5
... Test Mode Select JTAGSEL JTAG Selection NRST Microcontroller Reset TST Test Mode Select DRXD Debug Receive Data DTXD Debug Transmit Data 6042E–ATARM–14-Dec-06 AT91SAM7A3 Preliminary Active Type Power Power Power Power Power Power Ground Clocks, Oscillators and PLLs Input Output ...
Page 6
... TF0 - TF1 Transmit Frame Sync RF0 - RF1 Receive Frame Sync TCLK0 - TCLK8 External Clock Input TIOA0 - TIOA8 I/O Line A TIOB0 - TIOB8 I/O Line B PWM0 - PWM7 PWM Channels AT91SAM7A3 Preliminary 6 Active Type AIC Input Input PIO I/O I/O Multimedia Card Interface Output ...
Page 7
... Two-wire Serial Clock ADC0_AD0 - ADC0_AD7 Analog Inputs ADC1_AD0 - ADC1_AD7 ADVREFP Analog Positive Reference ADC0_ADTRG ADC Trigger ADC1_ADTRG CANRX0-CANRX1 CAN Inputs CANTX0-CANTX1 CAN Outputs 6042E–ATARM–14-Dec-06 AT91SAM7A3 Preliminary Active Type Level SPI I/O I/O I/O I/O Output Two-wire Interface I/O I/O Analog-to-Digital Converter ...
Page 8
... Package 4.1 100-lead LQFP Package Outline Figure 4-1 description is given in the Mechanical Characteristics section of the full datasheet. Figure 4-1. AT91SAM7A3 Preliminary 8 shows the orientation of the 100-lead LQFP package. A detailed mechanical 100-lead LQFP Outline (Top View 100 6042E–ATARM–14-Dec-06 ...
Page 9
... GND 41 17 VDD1V8 42 18 PB2 43 19 PB1 44 20 PB0 45 21 PA0 46 22 PA1 47 23 PA2 48 24 PA3 49 25 GND 50 6042E–ATARM–14-Dec-06 AT91SAM7A3 Preliminary VDDBU 51 FWKUP 52 WKUP0 53 WKUP1 54 SHDW 55 GND 56 PA4 57 PA5 58 PA6 59 VDD1V8 PA7 60 PA8 61 VDD3V3 PA9 62 VDD3V3 63 GND 64 VDD1V8 ...
Page 10
... Voltage Regulator The AT91SAM7A3 embeds a voltage regulator that consumes less than 120 µA static current and draws up to 130 mA of output current. Adequate output supply decoupling is mandatory for VDD1V8 (pin 99)to reduce ripple and avoid oscillations ...
Page 11
... Typical Powering Schematics 5.3.1 3.3V Single Supply The AT91SAM7A3 supports a 3.3V single supply mode. The internal regulator is connected to the 3.3V source and its output feeds VDDPLL. used for USB bus-powered systems. Figure 5-1. 6042E–ATARM–14-Dec-06 AT91SAM7A3 Preliminary Figure 5-1 3 ...
Page 12
... The FWUP, WKUP0 and WKUP1 pins are input-only. They can accept voltages only between 0V and VDDBU recommended to tie these pins either to GND or to VDDBU with an exter- nal resistor. 6.6 I/O Line Drive Levels All the I/O lines can draw mA. AT91SAM7A3 Preliminary 12 6042E–ATARM–14-Dec-06 ...
Page 13
... Facilitates debug by detection of bad pointers – Alignment checking of all data accesses – Abort generation in case of misalignment – Remaps the Internal SRAM in place of the embedded non-volatile memory – Allows handling of dynamic exception vectors – Individually programmable size between 1K Bytes and 1M Bytes AT91SAM7A3 Preliminary 13 ...
Page 14
... Handles data transfer between peripherals and memories • Nineteen Channels • Low bus arbitration overhead • Next Pointer management for reducing interrupt latency requirements AT91SAM7A3 Preliminary 14 – Individually programmable protection against write and/or user access – Peripheral protection against write and/or user access – ...
Page 15
... Fast access time, 30 MHz single cycle access in worst case conditions. – Page programming time: 6 ms, including page auto-erase – Full erase time – 10,000 write cycles, 10-year data retention capability – 16 lock bits, each protecting 16 pages – Single-cycle access at full speed AT91SAM7A3 Preliminary 15 ...
Page 16
... Figure 8-1. AT91SAM7A3 Memory Mapping Address Memory Space 0x0000 0000 Internal Memories 256 MBytes 0x0FFF FFFF 0x1000 0000 Undefined 14 x 256 MBytes (Abort) 3,584 MBytes 0xEFFF FFFF 0xF000 0000 Internal Peripherals 256 MBytes 0xFFFF FFFF AT91SAM7A3 Preliminary 16 Internal Memory Mapping 0x0000 0000 ...
Page 17
... Embedded Flash 8.3.1 Flash Overview The Flash block of the AT91SAM7A3 is organized in 1024 pages of 256 bytes. It reads as 65,536 32-bit words. The Flash block contains a 256-byte write buffer, accessible through a 32-bit interface. When Flash is not used (read or write access automatically put into standby mode. ...
Page 18
... The Embedded Flash Controller manages 16 lock bits to protect 16 regions of the Flash against inadvertent Flash erasing or programming commands. The AT91SAM7A3 has 16 lock regions. Each lock region contains 16 pages of 256 bytes. Each lock region has a size of 4 Kbytes, thus only the first 64 Kbytes can be locked. ...
Page 19
... Figure 9-1 on page 20 Figure 8-1 on page 16 peripherals. Note that the Memory Controller configuration user interface is also mapped within this address space. 6042E–ATARM–14-Dec-06 AT91SAM7A3 Preliminary shows the System Controller Block Diagram. shows the mapping of the User Interface of the System Controller 19 ...
Page 20
... VDDBU Powered RCOSC XIN MAIN OSC XOUT PLL PLLRC periph_nreset periph_nreset proc_nreset periph_nreset periph_clk[2..3] dbgu_rxd PA0-PA31 PB0-PB29 9.1 System Controller Mapping AT91SAM7A3 Preliminary 20 System Controller fiq Advanced Interrupt int Controller MCK dbgu_irq Debug Unit dbgu_txd wdt_fault WDRPROC periph_nreset ice_nreset proc_nreset jtag_nreset ...
Page 21
... XIN XOUT PLLRC – the Processor Clock PCK – the Master Clock MCK – the USB Clock UDPCK – all the peripheral clocks, independently controllable – four programmable clock outputs AT91SAM7A3 Preliminary Clock Generator Embedded Slow Clock RC SLCK Oscillator Main Main Clock ...
Page 22
... Controls the interrupt lines (nIRQ and nFIQ) of the ARM Processor • Individually maskable and vectored interrupt sources • 8-level Priority Controller • Vectoring • Protect Mode • Fast Forcing • General Interrupt Mask AT91SAM7A3 Preliminary 22 Power Management Controller Block Diagram Master Clock Controller SLCK Prescaler MAINCK /1,/2,/4, ...
Page 23
... Offers visibility of COMMRX and COMMTX signals from the ARM Processor – Identification of the device revision, sizes of the embedded memories, set of peripherals – Chip ID is 0x260A0941 (Version 1) – Input change interrupt – Half a clock period Glitch filter – Multi-drive option enables driving in open drain AT91SAM7A3 Preliminary 23 ...
Page 24
... Programmable pull up on each I/O line – Pin data status register, supplies visibility of the level on the pin at any time • Synchronous output, provides Set and Clear of several I/O lines in a single write AT91SAM7A3 Preliminary 24 6042E–ATARM–14-Dec-06 ...
Page 25
... Peripherals 10.1 Peripheral Mapping Each User Peripheral is allocated 16K bytes of address space. Figure 10-1. User Peripherals Mapping 6042E–ATARM–14-Dec-06 AT91SAM7A3 Preliminary Address Peripheral Peripheral Name 0xF000 0000 Reserved 0xFFF7 FFFF 0xFFF8 0000 CAN0 CAN Controller 0 0xFFF8 3FFF 0xFFF8 4000 CAN1 ...
Page 26
... Peripheral Multiplexing on PIO Lines The AT91SAM7A3 features two PIO controllers, PIOA and PIOB, which multiplex the I/O lines of the peripheral set. PIO Controllers A and B control respectively 32 and 30 lines. Each line can be assigned to one of two peripheral functions Some of them can also be multiplexed with Analog Input of both ADC Controllers ...
Page 27
... DRXD PA31 DTXD 6042E–ATARM–14-Dec-06 Peripheral B Comment ADC0_ADTRG ADC1_ADTRG SPI1_NPSC0 SPI1_NPCS1 SPI1_NPCS2 SPI1_NPCS3 SPI1_MISO SPI1_MOSI SPI1_SPCK MCDA1 MCDA2 MCDA3 MCDA0 MCCDA MCCK PCK0 PCK1 PCK2 PCK3 IRQ0 IRQ1 TCLK4 TCLK5 TCLK3 TCLK6 TCLK7 TCLK8 AT91SAM7A3 Preliminary Application Usage Function Comments 27 ...
Page 28
... PB20 TIOA4 PB21 TIOB4 PB22 TIOA5 PB23 TIOB5 PB24 TIOA6 PB25 TIOB6 PB26 TIOA7 PB27 TIOB7 PB28 TIOA8 PB29 TIOB8 AT91SAM7A3 Preliminary 28 Peripheral B Comment PWM5 PWM6 PWM7 PCK0 PCK1 PCK2 PCK3 CANTX1 TF1 TK1 RK1 RF1 TD1 RD1 PWM0 ADC0_AD0 PWM1 ...
Page 29
... Peripheral Identifiers The AT91SAM7A3 embeds a wide range of peripherals. Identifiers of the AT91SAM7A3. Unique peripheral identifiers are defined for both the AIC and the PMC. Table 11-1. Peripheral Note: 6042E–ATARM–14-Dec-06 Peripheral Identifiers Peripheral Peripheral Mnemonic Name AIC Advanced Interrupt Controller (1) SYSC ...
Page 30
... RS485 with driver control signal • ISO7816 Protocols for interfacing with smart cards • IrDA modulation and demodulation • Test Modes AT91SAM7A3 Preliminary 30 – Four chip selects with external decoder allow communication with peripherals – Serial memories, such as DataFlash – ...
Page 31
... TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 – Two multi-purpose input/output signals – Two global registers that act on all three TC Channels – A Modulo n counter providing eleven clocks – Two independent linear dividers working on modulo n counter outputs AT91SAM7A3 Preliminary Table 11-2. Clock MCK/2 MCK/8 MCK/32 MCK/128 ...
Page 32
... CAN Controller • Fully compliant with CAN 2.0B active controllers • Bit rates up to 1Mbit/s • 16 object-oriented mailboxes, each with the following properties: AT91SAM7A3 Preliminary 32 – Independent enable/disable commands – Independent clock selection – Independent period and duty cycle, with double buffering – ...
Page 33
... Low power mode and programmable wake-up on bus activity or by the application – Data, remote, error and overload frame handling – Hardware or software trigger – External pins: ADTRG0 and ADTRG1 – Timer Counter outputs: TIOA0 to TIOA5 – Automatic wakeup on trigger and back to sleep mode after conversions of all enabled channels AT91SAM7A3 Preliminary 33 ...
Page 34
... AT91SAM7A3 Preliminary 34 6042E–ATARM–14-Dec-06 ...
Page 35
... FIQ: Designed to support high-speed data transfer or channel process IRQ: Used for general-purpose interrupt handling Supervisor: Protected mode for the operating system Abort mode: Implements virtual memory and/or memory protection System: A privileged user mode for the operating system Undefined: Supports software emulation of hardware coprocessors AT91SAM7A3 Preliminary 35 ...
Page 36
... R14 holds the return address after a subroutine call. R13 is used (by software convention stack pointer Table 12-1. User and System Mode R10 R11 R12 R13 R14 PC CPSR AT91SAM7A3 Preliminary 36 ARM7TDMI ARM Modes and Registers Layout Supervisor Undefined Mode Abort Mode Mode ...
Page 37
... More than one exception can occur in the same time. When an exception occurs, the banked version of R14 and the SPSR for the exception mode are used to save state. 6042E–ATARM–14-Dec-06 AT91SAM7A3 Preliminary supports five types of exception and a privileged processing mode for each 37 ...
Page 38
... To return after handling the exception, the SPSR is moved to the CPSR, and R14 is moved to the PC. This can be done in two ways: • by using a data-processing instruction with the S-bit set, and the PC as the destination • by using the Load Multiple with Restore CPSR instruction (LDM) AT91SAM7A3 Preliminary 38 6042E–ATARM–14-Dec-06 ...
Page 39
... BX LDR LDRSH LDRSB LDRH LDRB LDRBT LDRT LDM SWP MCR LDC 6042E–ATARM–14-Dec-06 AT91SAM7A3 Preliminary gives the ARM instruction mnemonic list. ARM Instruction Mnemonic List Operation Move Add Subtract Reverse Subtract Compare Test Logical AND Logical Exclusive OR Multiply Sign Long Multiply ...
Page 40
... TST AND EOR LSL ASR MUL B BX LDR LDRH LDRB LDRSH LDMIA PUSH AT91SAM7A3 Preliminary 40 gives the Thumb instruction mnemonic list. Thumb Instruction Mnemonic List Operation Move Add Subtract Compare Test Logical AND Logical Exclusive OR Logical Shift Left Arithmetic Shift Right ...
Page 41
... AT91SAM7A3 Debug and Test Features 13.1 Overview The AT91SAM7A3 features a number of complementary debug and test capabilities. A com- mon JTAG/ICE (Embedded ICE) port is used for standard debugging functions, such as downloading code and single-stepping through programs. The Debug Unit provides a two-pin UART that can be used to upload an application into internal SRAM. It manages the interrupt handling of the internal COMMTX and COMMRX signals that trace the activity of the Debug Communication Channel ...
Page 42
... Figure 13-2. Application Debug Environment Example AT91SAM7A3 Preliminary 42 shows a complete debug environment example. The ICE/JTAG inter- ICE/JTAG Interface ICE/JTAG Connector RS232 AT91SAM7A3 Connector AT91SAM7A3-based Application Board Host Debugger Terminal 6042E–ATARM–14-Dec-06 ...
Page 43
... Test vectors are sent and inter- Test Adaptor JTAG Interface ICE/JTAG Chip n Chip 2 Connector AT91SAM7A3 Chip 1 AT91SAM7A3-based Application Board In Test Debug and Test Pin List Function Reset/Test Microcontroller Reset Test Mode Select ICE and JTAG Test Clock Test Data In Test Data Out ...
Page 44
... XMODEM. A specific register, the Debug Unit Chip ID Register, gives information about the product ver- sion and its internal configuration. The AT91SAM7A3 Debug Unit Chip ID value is 0x260A0941 on 32-bit width. For further details on the Debug Unit, see the Debug Unit section. AT91SAM7A3 Preliminary 44 6042E– ...
Page 45
... The Boundary-scan Register (BSR) contains 186 bits that correspond to active pins and asso- ciated control signals. Each AT91SAM7A3 input/output pin corresponds to a 3-bit register in the BSR. The OUTPUT bit contains data that can be forced on the pad. The INPUT bit facilitates the observability of data applied to the pad ...
Page 46
... Table 13-2. Bit Number AT91SAM7A3 Preliminary 46 AT91SAM7A3 JTAG Boundary Scan Register (Continued) Pin Name 167 166 PB7 165 164 163 PB6 162 161 160 PB5 159 158 157 PB4 156 155 154 PB3 153 152 151 PB2 150 149 148 PB1 ...
Page 47
... Table 13-2. Bit Number 6042E–ATARM–14-Dec-06 AT91SAM7A3 JTAG Boundary Scan Register (Continued) Pin Name 134 133 PA3 132 131 130 PA4 129 128 127 PA5 126 125 124 PA6 123 122 121 PA7 120 119 118 PA8 117 116 115 ...
Page 48
... Table 13-2. Bit Number AT91SAM7A3 Preliminary 48 AT91SAM7A3 JTAG Boundary Scan Register (Continued) Pin Name 101 100 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 69 Associated BSR Pin Type Cells INPUT IN/OUT OUTPUT CONTROL INPUT IN/OUT OUTPUT CONTROL INPUT ...
Page 49
... Table 13-2. Bit Number 6042E–ATARM–14-Dec-06 AT91SAM7A3 JTAG Boundary Scan Register (Continued) Pin Name 68 67 PA25 PA26 PA27 PA28 PA29 PA30 PA31 PB14 PB15 PB16 PB17 36 AT91SAM7A3 Preliminary Associated BSR Pin Type IN/OUT CONTROL IN/OUT CONTROL IN/OUT CONTROL IN/OUT CONTROL ...
Page 50
... Table 13-2. Bit Number AT91SAM7A3 Preliminary 50 AT91SAM7A3 JTAG Boundary Scan Register (Continued) Pin Name 35 34 PB18 PB19 PB20 PB21 PB22 PB23 PB24 PB25 PB26 PB27 PB28 3 Associated BSR Pin Type Cells INPUT IN/OUT OUTPUT CONTROL INPUT IN/OUT OUTPUT CONTROL INPUT IN/OUT ...
Page 51
... Table 13-2. Bit Number 6042E–ATARM–14-Dec-06 AT91SAM7A3 JTAG Boundary Scan Register (Continued) Pin Name 2 1 PB29 0 AT91SAM7A3 Preliminary Associated BSR Pin Type IN/OUT CONTROL Cells INPUT OUTPUT 51 ...
Page 52
... PART NUMBER 7 6 • VERSION[31:28]: Product Version Number Set to 0x1. • PART NUMBER[27:12]: Product Part Number Product part Number is 0x5B05 • MANUFACTURER IDENTITY[11:1] Set to 0x01F. Bit[0] Required by IEEE Std. 1149.1. Set to 0x1. JTAG ID Code value is 0x05B0503F AT91SAM7A3 Preliminary PART NUMBER ...
Page 53
... The NRST Manager shapes the NRST assertion during a programmable time, thus controlling external device resets. 6042E–ATARM–14-Dec-06 Reset Controller Main Supply POR Startup POR Counter NRST NRST Manager nrst_out WDRPROC wd_fault AT91SAM7A3 Preliminary rstc_irq Reset State Manager proc_nreset user_reset periph_nreset exter_nreset backup_neset SLCK 53 ...
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... NRST Manager for a time programmed by the field ERSTL in RSTC_MR. This assertion duration, named EXTERNAL_RESET_LENGTH, lasts 2 between 60 µs and 2 seconds. Note that ERSTL at 0 defines a two-cycle duration for the NRST pulse. AT91SAM7A3 Preliminary 54 Figure 14-2 shows the block diagram of the NRST Manager. RSTC_SR ...
Page 55
... MCK Backup Supply POR output backup_nreset proc_nreset RSTTYP periph_nreset NRST (nrst_out) 6042E–ATARM–14-Dec-06 shows how the General Reset affects the reset signals. Startup Time Processor Startup = 3 cycles XXX EXTERNAL RESET LENGTH = 2 cycles AT91SAM7A3 Preliminary Any Freq. 0x0 = General Reset XXX 55 ...
Page 56
... The User Reset is left when NRST rises, after a two-cycle resynchronization time and a three- cycle processor startup. The processor clock is re-enabled as soon as NRST is confirmed high. When the processor reset signal is released, the RSTTYP field of the Status Register (RSTC_SR) is loaded with the value 0x4, indicating a User Reset. AT91SAM7A3 Preliminary 56 SLCK MCK POR output Resynch ...
Page 57
... Master Clock (MCK). They are released when the software reset is left, i.e.; synchronously to SLCK. If EXTRST is set, the nrst_out signal is asserted depending on the programming of the field ERSTL. However, the resulting falling edge on NRST does not lead to a User Reset. 6042E–ATARM–14-Dec-06 AT91SAM7A3 Preliminary Resynch. 2 cycles XXX >= EXTERNAL RESET LENGTH ...
Page 58
... WDRSTEN is set, the Watchdog Timer is always reset after a Watchdog Reset, and the Watchdog is enabled by default and with a period set to a maximum. When the WDRSTEN in WDT_MR bit is reset, the watchdog fault has no impact on the reset controller. AT91SAM7A3 Preliminary 58 SLCK Any MCK Freq ...
Page 59
... A software reset is impossible, since the processor reset is being activated. – A watchdog event has priority over the current state. – The NRST has no effect. – The processor reset is active and so a Software Reset cannot be programmed. – A User Reset cannot be entered. AT91SAM7A3 Preliminary Processor Startup = 3 cycles XXX 0x2 = Watchdog Reset ...
Page 60
... URSTIEN bit in the RSTC_MR register, the URSTS bit triggers an interrupt. Reading the RSTC_SR status register resets the URSTS bit and clears the interrupt. Figure 14-8. Reset Controller Status and Interrupt MCK Peripheral Access 2 cycle resynchronization NRST NRSTL URSTS rstc_irq if (URSTEN = 0) and (URSTIEN = 1) AT91SAM7A3 Preliminary 60 read RSTC_SR 2 cycle resynchronization 6042E–ATARM–14-Dec-06 Figure ...
Page 61
... Control Register 0x04 Status Register 0x08 Mode Register Note: 1. The reset value of RSTC_SR either reports a General Reset or a Wake-up Reset depending on last rising power supply. 6042E–ATARM–14-Dec-06 AT91SAM7A3 Preliminary Name Access RSTC_CR Write-only RSTC_SR Read-only RSTC_MR Read/Write Back-up Reset ...
Page 62
... PERRST: Peripheral Reset effect KEY is correct, resets the peripherals. • EXTRST: External Reset effect KEY is correct, asserts the NRST pin. • KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation. AT91SAM7A3 Preliminary 62 RSTC_CR Write-only KEY ...
Page 63
... Comments Both VDD1V8 and VDDBU rising VDD1V8 rising Watchdog fault occurred Processor reset required by the software NRST pin detected low AT91SAM7A3 Preliminary 26 25 – – – SRCMP 10 9 RSTTYP 2 1 – 24 – 16 NRSTL 8 ...
Page 64
... This field defines the external reset length. The external reset is asserted during a time of 2 allows assertion duration to be programmed between 60 µs and 2 seconds. • KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation. AT91SAM7A3 Preliminary 64 RSTC_MR Read/Write ...
Page 65
... Thus if the RTT is configured to trigger an interrupt, the interrupt occurs during 2 Slow Clock cycles after reading RTT_SR. To prevent several executions of the interrupt handler, the interrupt must be disabled in the interrupt handler and re-enabled when the status register is clear. 6042E–ATARM–14-Dec-06 AT91SAM7A3 Preliminary set 0 RTT_SR RTTINC ...
Page 66
... RTPRES - 1 RTTINC (RTT_SR) ALMS (RTT_SR) APB Interface AT91SAM7A3 Preliminary 66 Because of the asynchronism between the Slow Clock (SCLK) and the System Clock (MCK): 1) The restart of the counter and the reset of the RTT_VR current value register is effective only 2 slow clock cycles after the write of the RTTRST bit in the RTT_MR register. ...
Page 67
... Real-time Timer (RTT) User Interface Table 15-1. Real-time Timer (RTT) Register Mapping Offset Register 0x00 Mode Register 0x04 Alarm Register 0x08 Value Register 0x0C Status Register 6042E–ATARM–14-Dec-06 AT91SAM7A3 Preliminary Name Access RTT_MR Read/Write RTT_AR Read/Write RTT_VR Read-only RTT_SR Read-only Reset Value 0x0000_8000 0xFFFF_FFFF ...
Page 68
... RTTINCIEN: Real-time Timer Increment Interrupt Enable 0 = The bit RTTINC in RTT_SR has no effect on interrupt The bit RTTINC in RTT_SR asserts interrupt. • RTTRST: Real-time Timer Restart 1 = Reloads and restarts the clock divider with the new programmed value. This also resets the 32-bit counter. AT91SAM7A3 Preliminary 68 RTT_MR Read/Write 29 ...
Page 69
... Defines the alarm value (ALMV+1) compared with the Real-time Timer. 15.4.3 Real-time Timer Value Register Register Name: Access Type • CRTV: Current Real-time Value Returns the current value of the Real-time Timer. 6042E–ATARM–14-Dec-06 RTT_AR Read/Write ALMV ALMV ALMV ALMV RTT_VR Read-only CRTV CRTV CRTV CRTV AT91SAM7A3 Preliminary ...
Page 70
... The Real-time Alarm occurred since the last read of RTT_SR. • RTTINC: Real-time Timer Increment 0 = The Real-time Timer has not been incremented since the last read of the RTT_SR The Real-time Timer has been incremented since the last read of the RTT_SR. AT91SAM7A3 Preliminary 70 RTT_SR Read-only ...
Page 71
... Status Register (PIT_SR) rises and triggers an interrupt, provided the interrupt is enabled (PITIEN in PIT_MR). Writing a new PIV value in PIT_MR does not reset/restart the counters. 6042E–ATARM–14-Dec-06 PIT_MR PIV = ? 0 1 PIT_PIVR PIT_PIIR AT91SAM7A3 Preliminary set 0 PIT_SR PITS reset 0 1 12-bit Adder read PIT_PIVR ...
Page 72
... The PIT is stopped when the core enters debug state. Figure 16-2. Enabling/Disabling PIT with PITEN 15 MCK Prescaler 0 PITEN CPIV 0 PICNT PITS (PIT_SR) APB Interface AT91SAM7A3 Preliminary 72 APB cycle MCK 1 PIV - 1 PIV 1 0 read PIT_PIVR Figure 16-2 APB cycle restarts MCK Prescaler ...
Page 73
... The bit PITS in PIT_SR has no effect on interrupt The bit PITS in PIT_SR asserts interrupt. 6042E–ATARM–14-Dec-06 Name PIT_MR PIT_SR PIT_PIVR PIT_PIIR – – – – – PIV PIV AT91SAM7A3 Preliminary Access Read/Write 0x000F_FFFF Read-only 0x0000_0000 Read-only 0x0000_0000 Read-only 0x0000_0000 26 25 – PITIEN 18 17 PIV Reset Value 24 PITEN ...
Page 74
... PITS: Periodic Interval Timer Status 0 = The Periodic Interval timer has not reached PIV since the last read of PIT_PIVR The Periodic Interval timer has reached PIV since the last read of PIT_PIVR. AT91SAM7A3 Preliminary – – – – ...
Page 75
... Reading this register clears PITS in PIT_SR. • CPIV: Current Periodic Interval Value Returns the current value of the periodic interval timer. • PICNT: Periodic Interval Counter Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR. 6042E–ATARM–14-Dec- PICNT CPIV CPIV AT91SAM7A3 Preliminary CPIV ...
Page 76
... Register Name: PIT_PIIR Access Type: Read-only PICNT • CPIV: Current Periodic Interval Value Returns the current value of the periodic interval timer. • PICNT: Periodic Interval Counter Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR. AT91SAM7A3 Preliminary PICNT CPIV CPIV ...
Page 77
... WDT_MR WDT_CR WDRSTT WDT_MR read WDT_SR or reset 6042E–ATARM–14-Dec-06 WDT_MR WDV reload 1 0 12-bit Down Counter WDD Current Value <= WDD = 0 set WDUNF reset set WDERR reset AT91SAM7A3 Preliminary reload SLCK 1/128 WDT_MR WDRSTEN wdt_fault (to Reset Controller) wdt_int WDFIEN WDT_MR 77 ...
Page 78
... Writing the WDT_MR reloads and restarts the down counter. While the processor is in debug state or in idle mode, the counter may be stopped depending on the value programmed for the bits WDIDLEHLT and WDDBGHLT in the WDT_MR. AT91SAM7A3 Preliminary 78 6042E–ATARM–14-Dec-06 ...
Page 79
... Figure 17-2. Watchdog Behavior FFF Normal behavior WDV Forbidden Window WDD Permitted Window 0 Watchdog Fault 6042E–ATARM–14-Dec-06 AT91SAM7A3 Preliminary Watchdog Error WDT_CR = WDRSTT Watchdog Underflow if WDRSTEN WDRSTEN ...
Page 80
... WDRSTT: Watchdog Restart 0: No effect. 1: Restarts the Watchdog. • KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation. AT91SAM7A3 Preliminary 80 Name WDT_CR WDT_MR WDT_SR KEY – – ...
Page 81
... The Watchdog runs when the system is in idle mode. 1: The Watchdog stops when the system is in idle state. • WDDIS: Watchdog Disable 0: Enables the Watchdog Timer. 1: Disables the Watchdog Timer. 6042E–ATARM–14-Dec- WDDBGHLT WDD WDFIEN WDV AT91SAM7A3 Preliminary 26 25 WDD WDV ...
Page 82
... No Watchdog underflow occurred since the last read of WDT_SR least one Watchdog underflow occurred since the last read of WDT_SR. • WDERR: Watchdog Error 0: No Watchdog error occurred since the last read of WDT_SR least one Watchdog error occurred since the last read of WDT_SR. AT91SAM7A3 Preliminary – ...
Page 83
... RTT Alarm 6042E–ATARM–14-Dec-06 read SYSC_SHSR reset WAKEUP0 SYSC_SHSR set read SYSC_SHSR reset SYSC_SHSR WAKEUP1 set read SYSC_SHSR reset SYSC_SHMR RTTWK SYSC_SHSR set FWKUP AT91SAM7A3 Preliminary SLCK Wake-up Shutdown Output Controller SYSC_SHCR Shutdown SHDW read SYSC_SHSR reset FWKUP SYSC_SHSR set SHDW 83 ...
Page 84
... RTT alarm is synchronized with SLCK). This is done by writing the SHDW_MR register using the RTTWKEN fields. When enabled, the detec- tion of the RTT alarm is reported in the RTTWK bit of the SHDW_SR Status register reset AT91SAM7A3 Preliminary 84 I/O Lines Description ...
Page 85
... The pin FWKUP is treated differently and a low level on this pin forces a de-assertion of the SHDW pin, regardless of the presence of the Slow Clock. The bit FWKUP in the status register reports a Forced Wakeup Event after internal resynchronization of the event with the Slow Clock. 6042E–ATARM–14-Dec-06 AT91SAM7A3 Preliminary 85 ...
Page 86
... SHDW: Shut Down Command effect KEY is correct, asserts the SHDW pin. • KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation. AT91SAM7A3 Preliminary 86 Name SHDW_CR SHDW_MR SHDW_SR KEY – ...
Page 87
... Wake-up Input Transition Selection None. No detection is performed on the wake-up input Low to high level High to low level Both levels change AT91SAM7A3 Preliminary 26 25 – – – – – – – – WKMODE1 – – WKMODE0 24 – ...
Page 88
... At least one wake-up event occurred on the Force Wake Up input since the last read of SHDW_SR. • RTTWK: Real-time Timer Wake- wake-up alarm from the RTT occurred since the last read of SHDW_SR least one wake-up alarm from the RTT occurred since the last read of SHDW_SR. AT91SAM7A3 Preliminary – ...
Page 89
... Access to peripherals can be protected in the same way. 19.2 Block Diagram Figure 19-1. Memory Controller Block Diagram ARM7TDMI Processor Abort Peripheral Data Controller 6042E–ATARM–14-Dec-06 AT91SAM7A3 Preliminary Memory Controller ASB Abort Status Address Misalignment Decoder Bus Detector Arbiter Memory ...
Page 90
... One 256-Mbyte address space reserved for the embedded peripherals • An undefined address space of 3584M bytes representing fourteen 256-Mbyte areas that return an Abort if accessed Figure 19-2 Figure 19-2. Memory Areas AT91SAM7A3 Preliminary 90 shows the assignment of the 256-Mbyte memory areas. 0x0000 0000 256M Bytes ...
Page 91
... Internal Memory Area 0 0x000F FFFF 0x0010 0000 Internal Memory Area 1 Internal Flash 0x001F FFFF 0x0020 0000 Internal Memory Area 2 256M Bytes Internal SRAM 0x002F FFFF 0x0030 0000 Undefined Areas 0x0FFF FFFF AT91SAM7A3 Preliminary 1M Bytes 1M Bytes 1M Bytes 253M bytes (Abort) 91 ...
Page 92
... The base address is also programmable on a number of bits according to the size. The Memory Protection Unit also allows the protection of the peripherals by programming the Protection Unit Peripheral Register (MC_PUP) with the field PROT at the appropriate value. AT91SAM7A3 Preliminary 92 Figure 6042E–ATARM–14-Dec-06 ...
Page 93
... These bugs are particularly difficult to detect in the debug phase. As the requested address is saved in the Abort Status Register and the address of the instruc- tion generating the misalignment is saved in the Abort Link Register of the processor, detection and fix of this kind of software bugs is simplified. 6042E–ATARM–14-Dec-06 AT91SAM7A3 Preliminary 93 ...
Page 94
... MC Protection Unit Area 12 0x44 MC Protection Unit Area 13 0x48 MC Protection Unit Area 14 0x4C MC Protection Unit Area 15 0x50 MC Protection Unit Peripherals 0x54 MC Protection Unit Enable Register 0x60 EFC Configuration Registers AT91SAM7A3 Preliminary 94 Name Access MC_RCR Write-only MC_ASR Read-only MC_AASR Read-only MC_PUIA0 Read/Write MC_PUIA1 ...
Page 95
... This Command Bit acts on a toggle basis: writing a 1 alternatively cancels and restores the remapping of the page zero memory devices. 6042E–ATARM–14-Dec- – – – – – – – – – – – – AT91SAM7A3 Preliminary 26 25 – – – – – – – – 24 – 16 – 8 – 0 RCB 95 ...
Page 96
... ABTSZ: Abort Size Status ABTSZ • ABTTYP: Abort Type Status ABTTYP • MST0: PDC Abort Source 0: The last aborted access was not due to the PDC. 1: The last aborted access was due to the PDC. AT91SAM7A3 Preliminary – – – – – – – – – ...
Page 97
... At least one abort due to the ARM7TDMI occurred. 19.4.3 MC Abort Address Status Register Register Name: MC_AASR Access Type: Read-only Reset Value: 0x0 Absolute Address: 0xFFFF FF08 • ABTADD: Abort Address This field contains the address of the last aborted access. 6042E–ATARM–14-Dec- ABTADD ABTADD ABTADD ABTADD AT91SAM7A3 Preliminary ...
Page 98
... BA: Internal Area Base Address These bits define the Base Address of the area. Note that only the most significant bits of BA are significant. The number of significant bits are in respect with the size of the area. AT91SAM7A3 Preliminary – – – – Processor Mode ...
Page 99
... Read/Write 1 0 Read/Write 1 1 Read/Write 6042E–ATARM–14-Dec- – – – – – – – – Processor Mode Privilege User No access No access Read-only Read/Write AT91SAM7A3 Preliminary – – – – – – – – – – – 24 – 16 – 8 – 0 PROT ...
Page 100
... Absolute Address: 0xFFFFFF54 31 30 – – – – – – – – • PUEB: Protection Unit Enable Bit 0: The Memory Controller Protection Unit is disabled. 1: The Memory Controller Protection Unit is enabled. AT91SAM7A3 Preliminary 100 – – – – – – – – – 5 ...
Page 101
... The Embedded Flash size, the page size and the lock region organization are described in the product definition section. 6042E–ATARM–14-Dec-06 AT91SAM7A3 Preliminary ”Read Operations” on page ”Write Operations” on page 104). ...
Page 102
... The Flash memory is accessible through 8-, 16- and 32-bit reads. As the Flash block size is smaller than the address space reserved for the internal memory area, the embedded Flash wraps around the address space and appears to be repeated within it. AT91SAM7A3 Preliminary 102 Flash Memory Lock Region 0 ...
Page 103
... Bytes 6-7 1 Wait State Cycle @Byte 6 @Byte 2 @Byte 4 Bytes 0-3 Bytes 4-7 Bytes 0-3 Bytes 0-1 Bytes 2-3 Bytes 4-5 AT91SAM7A3 Preliminary @Byte 10 @Byte 12 @Byte 14 Bytes 12-15 Bytes 8-11 Bytes 12-15 Bytes 8-9 Bytes 10-11 Bytes 12-13 1 Wait State Cycle 1 Wait State Cycle ...
Page 104
... Write Page and Lock Clear Lock Bit Erase all In order to perform one of these commands, the Flash Command Register (MC_FCR) has to be written with the correct command using to the field FCMD (see ister” on page AT91SAM7A3 Preliminary 104 3 Wait State Cycles 3 Wait State Cycles @8 @6 ...
Page 105
... Figure 20-5. State of the EOP Bit in MC_FSR When the software reads the Flash Status Register (MC_FSR), the EOP bit is automatically cleared and the interrupt line is deactivated. 6042E–ATARM–14-Dec-06 110). Write the MC_FCR with WP or WPL command EOP Programming Time AT91SAM7A3 Preliminary Read the MC_FSR 105 ...
Page 106
... Lock Bit Command (SLB) or Clear Lock Bit Command (CLB)) in the Flash Command Register (MC_FCR). PAGEN defines one page number of the lock region to be locked or unlocked. Writing in all the other bits of PAGEN has no effect. AT91SAM7A3 Preliminary 106 Figure 20-6). ...
Page 107
... When the Flash erase is complete, the bit EOP in the Flash Programming Status Register rises interrupt has been enabled by setting the bit EOP in MC_FMR, the interrupt line of the Memory Controller is activated. 6042E–ATARM–14-Dec-06 AT91SAM7A3 Preliminary Write the MC_FCR with SLB, CLB or WPL command EOL Locking or unlocking Time Sequence Read the MC_FSR ” ...
Page 108
... MC_FCR register. • Lock Error: At least one lock region to be erased is protected. The erase command has been refused and no page has been erased. A Clear Lock Bit command must be executed previously to unlock the corresponding lock regions. AT91SAM7A3 Preliminary 108 6042E–ATARM–14-Dec-06 ...
Page 109
... Table 20-2. Embedded Flash Controller (EFC) Register Mapping Offset Register 0x60 MC Flash Mode Register 0x64 MC Flash Command Register 0x68 MC Flash Status Register 0x6C Reserved 6042E–ATARM–14-Dec-06 AT91SAM7A3 Preliminary Name Access MC_FMR Read/Write MC_FCR Write-only MC_FSR Read-only – – Reset State 0x0 – ...
Page 110
... Programming Error generates an interrupt. • NEBP: No Erase Before Programming 0: A page erase is performed before programming erase is performed before programming. • FWS: Flash Wait State This field defines the number of wait states for read and write operations: FWS AT91SAM7A3 Preliminary 110 – – – ...
Page 111
... When writing the rest of the Flash, this field defines the number of Master Clock cycles in 1.5 microseconds. This number must be rounded up. Warning: The value 0 is only allowed for a Master Clock period superior to 30 microseconds. Warning: In order to guarantee valid operations on the Flash memory, the field Flash Microsecond Cycle Number (FMCN) must be correctly programmed. 6042E–ATARM–14-Dec-06 AT91SAM7A3 Preliminary 111 ...
Page 112
... FCMD: Flash Command This field defines the Flash commands: FCMD 0000 0001 0010 0011 0100 1000 Others AT91SAM7A3 Preliminary 112 KEY – – – PAGEN – – Operations No command. Does not raise the Programming Error Status flag in the Flash Status Register MC_FSR. ...
Page 113
... This field should be written with the value 0x5A to enable the command defined by the bits of the register. If the field is writ- ten with a different value, the write is actually not performed and no action is started. 6042E–ATARM–14-Dec-06 AT91SAM7A3 Preliminary PAGEN Description PAGEN defines the page number to be written. ...
Page 114
... No invalid commands and no bad key-words were written in the Flash Command Register MC_FCR invalid command and/or a bad key-word was/were written in the Flash Command Register MC_FCR. • LOCKSx: Lock Region x Lock Status 0: The corresponding lock region is not locked. 1: The corresponding lock region is locked. AT91SAM7A3 Preliminary 114 ...
Page 115
... The peripheral triggers PDC transfers using transmit and receive signals. When the pro- grammed data is transferred, an end of transfer interrupt is generated by the corresponding peripheral. 21.2 Block Diagram Figure 21-1. Block Diagram 6042E–ATARM–14-Dec-06 AT91SAM7A3 Preliminary Peripheral DMA Controller Peripheral THR PDC Channel 0 PDC Channel 1 RHR Status & ...
Page 116
... When the counter reaches zero, the transfer is complete and the PDC stops transferring data. If the Next Counter Register is equal to zero, the PDC disables the trigger while activating the related peripheral end flag. AT91SAM7A3 Preliminary 116 6042E–ATARM–14-Dec-06 ...
Page 117
... If simultaneous requests of the same type (receiver or transmitter) occur on identical peripher- als, the priority is determined by the numbering of the peripherals. If transfer requests are not simultaneous, they are treated in the order they occurred. Requests from the receivers are handled first and then followed by transmitter requests. 6042E–ATARM–14-Dec-06 AT91SAM7A3 Preliminary 117 ...
Page 118
... PDC Transfer Status Register Note: 1. PERIPH: Ten registers are mapped in the peripheral memory space at the same offset. These can be defined by the user according to the function and the peripheral desired (DBGU, USART, SSC, SPI, MCI etc). AT91SAM7A3 Preliminary 118 Register Name Read/Write ...
Page 119
... RXPTR: Receive Pointer Address Address of the next receive transfer. 21.4.2 PDC Receive Counter Register Register Name: PERIPH_RCR Access Type: Read/Write • RXCTR: Receive Counter Value Number of receive transfers to be performed. 6042E–ATARM–14-Dec- RXPTR RXPTR RXPTR RXPTR RXCTR RXCTR AT91SAM7A3 Preliminary 119 ...
Page 120
... Address of the transmit buffer. 21.4.4 PDC Transmit Counter Register Register Name: PERIPH_TCR Access Type: Read/Write • TXCTR: Transmit Counter Value TXCTR is the size of the transmit transfer to be performed. At zero, the peripheral data transfer is stopped. AT91SAM7A3 Preliminary 120 TXPTR TXPTR TXPTR TXPTR ...
Page 121
... RXNPTR is the address of the next buffer to fill with received data when the current buffer is full. 21.4.6 PDC Receive Next Counter Register Register Name: PERIPH_RNCR Access Type: Read/Write • RXNCR: Receive Next Counter Value RXNCR is the size of the next buffer to receive. 6042E–ATARM–14-Dec- RXNPTR RXNPTR RXNPTR RXNPTR RXNCR RXNCR AT91SAM7A3 Preliminary 121 ...
Page 122
... TXNPTR is the address of the next buffer to transmit when the current buffer is empty. 21.4.8 PDC Transmit Next Counter Register Register Name: PERIPH_TNCR Access Type: Read/Write • TXNCR: Transmit Next Counter Value TXNCR is the size of the next buffer to transmit. AT91SAM7A3 Preliminary 122 TXNPTR TXNPTR TXNPTR ...
Page 123
... TXTDIS: Transmitter Transfer Disable effect Disables the transmitter PDC transfer requests 6042E–ATARM–14-Dec- – – – – – – – – – – – – AT91SAM7A3 Preliminary 26 25 – – – – – TXTDIS 2 1 – RXTDIS 24 – 16 – 8 TXTEN 0 RXTEN 123 ...
Page 124
... RXTEN: Receiver Transfer Enable 0 = Receiver PDC transfer requests are disabled Receiver PDC transfer requests are enabled. • TXTEN: Transmitter Transfer Enable 0 = Transmitter PDC transfer requests are disabled Transmitter PDC transfer requests are enabled. AT91SAM7A3 Preliminary 124 – – – ...
Page 125
... The fast forcing feature redirects any internal or external interrupt source to provide a fast interrupt rather than a normal interrupt. 22.2 Block Diagram Figure 22-1. Block Diagram 6042E–ATARM–14-Dec-06 AT91SAM7A3 Preliminary FIQ AIC IRQ0-IRQn Up to Thirty-two Sources Embedded ...
Page 126
... AIC Detailed Block Diagram Figure 22-3. AIC Detailed Block Diagram 22.5 I/O Line Description Table 22-1. I/O Line Description Pin Name FIQ IRQ0 - IRQn AT91SAM7A3 Preliminary 126 Standalone OS Drivers Applications General OS Interrupt Handler Advanced Interrupt Controller Embedded Peripherals Advanced Interrupt Controller ...
Page 127
... The peripheral identification defined at the product level corresponds to the interrupt source number (as well as the bit number controlling the clock of the peripheral). Consequently, to simplify the description of the functional operations and the user interface, the interrupt sources are named FIQ, SYS, and PID2 to PID31. 6042E–ATARM–14-Dec-06 AT91SAM7A3 Preliminary 127 ...
Page 128
... The AIC_ISR register reads the number of the current interrupt (see page the processor. Each status referred to above can be used to optimize the interrupt handling of the systems. AT91SAM7A3 Preliminary 128 (See “Priority Controller” on page 136.) 132) and the register AIC_CISR gives an image of the signals nIRQ and nFIQ driven on 132 ...
Page 129
... Level/ Source i Edge Edge Detector Set Clear AIC_ISCR AIC_ICCR AIC_SMRi SRCTYPE High/Low Pos./Neg. Edge Detector Set Clear AT91SAM7A3 Preliminary AIC_IPR AIC_IMR Fast Interrupt Controller or Priority Controller AIC_IECR FF AIC_IDCR Level/ AIC_IPR Edge AIC_IMR FF Fast Interrupt Controller or Priority Controller AIC_IECR AIC_IDCR ...
Page 130
... The PIO Controller multiplexing has no effect on the interrupt latencies of the external interrupt sources. 22.7.2.1 External Interrupt Edge Triggered Source Figure 22-6. AT91SAM7A3 Preliminary 130 External Interrupt Edge Triggered Source MCK IRQ or FIQ (Positive Edge) ...
Page 131
... External Interrupt Level Sensitive Source Figure 22-7. 22.7.2.3 Internal Interrupt Edge Triggered Source Figure 22-8. 22.7.2.4 Internal Interrupt Level Sensitive Source Figure 22-9. 6042E–ATARM–14-Dec-06 AT91SAM7A3 Preliminary External Interrupt Level Sensitive Source MCK IRQ or FIQ (High Level) IRQ or FIQ (Low Level) nIRQ Maximum IRQ ...
Page 132
... This feature offers a way to branch in one single instruction to the handler corresponding to the current interrupt, as AIC_IVR is mapped at the absolute address 0xFFFF F100 and thus accessible from the ARM interrupt vector at address 0x0000 0018 through the following instruction: AT91SAM7A3 Preliminary 132 6042E–ATARM–14-Dec-06 ...
Page 133
... Pushes the current level and the current interrupt number on to the stack. – Returns the value written in the AIC_SVR corresponding to the current interrupt. routine. This should start by saving the link register (R14_irq) and SPSR_IRQ. The link register must be decremented by four when it is saved restored AT91SAM7A3 Preliminary 133 ...
Page 134
... PC. This has the effect of returning from the interrupt to whatever was being executed before, and of loading the CPSR with the stored SPSR, masking or unmasking the interrupts depending on the state saved in SPSR_irq. Note: AT91SAM7A3 Preliminary 134 If the interrupt is programmed to be level sensitive, the source of the interrupt must be cleared during this phase. ...
Page 135
... FIQ link register (R14_FIQ) and the program counter (R15) is loaded with 0x1C. In the following cycle, during fetch at address 0x20, the ARM core adjusts R14_fiq, decrementing it by four. loaded with the value read in AIC_FVR. Reading the AIC_FVR has effect of automat- AT91SAM7A3 Preliminary 135 ...
Page 136
... The read of the FVR does not clear the Source 0 when the fast forcing feature is used and the interrupt source should be cleared by writing to the Interrupt Clear Command Register (AIC_ICCR). AT91SAM7A3 Preliminary 136 ically clearing the fast interrupt has been programmed to be edge triggered. In this case only, it de-asserts the nFIQ line on the processor ...
Page 137
... Fast Interrupt sources. Figure 22-10. Fast Forcing Source 0 _ FIQ Input Stage Automatic Clear Source n Input Stage Automatic Clear 6042E–ATARM–14-Dec-06 AT91SAM7A3 Preliminary AIC_IPR AIC_IMR Read FVR if Fast Forcing is disabled on Sources 1 to 31. AIC_FFSR AIC_IPR AIC_IMR Read IVR if Source n is the current interrupt and if Fast Forcing is disabled on Source n ...
Page 138
... AIC to assert the nIRQ, but no longer present when AIC_IVR is read. This is most prone to occur when: • An external interrupt source is programmed in level-sensitive mode and an active level occurs for only a short time. AT91SAM7A3 Preliminary 138 6042E–ATARM–14-Dec-06 ...
Page 139
... Idle Mode. This function facilitates synchronizing the processor on a next event and, as soon as the event occurs, performs subsequent operations without having to handle an interrupt strongly recommended to use this mask with caution. 6042E–ATARM–14-Dec-06 AT91SAM7A3 Preliminary 139 ...
Page 140
... The reset value of this register depends on the level of the external interrupt source. All other sources are cleared at reset, thus not pending. 2. PID2...PID31 bit fields refer to the identifiers as defined in the Peripheral Identifiers Section of the product datasheet. AT91SAM7A3 Preliminary 140 Name AIC_SMR0 ...
Page 141
... Internal Interrupt Sources High level Sensitive Positive edge triggered High level Sensitive Positive edge triggered AT91SAM7A3 Preliminary 26 25 – – – – – – PRIOR External Interrupt Sources Low level Sensitive Negative edge triggered ...
Page 142
... The Interrupt Vector Register contains the vector programmed by the user in the Source Vector Register corresponding to the current interrupt. The Source Vector Register is indexed using the current interrupt number when the Interrupt Vector Register is read. When there is no current interrupt, the Interrupt Vector Register reads the value stored in AIC_SPU. AT91SAM7A3 Preliminary 142 29 28 ...
Page 143
... IRQID: Current Interrupt Identifier The Interrupt Status Register returns the current interrupt source number. 6042E–ATARM–14-Dec- FIQV FIQV FIQV FIQV – – – – – – – – – – AT91SAM7A3 Preliminary – – – – – – IRQID – 16 – 8 – 0 143 ...
Page 144
... Access Type: Read-only Reset Value: 0x0 31 30 PID31 PID30 23 22 PID23 PID22 15 14 PID15 PID14 7 6 PID7 PID6 • FIQ, SYS, PID2-PID31: Interrupt Mask 0 = Corresponding interrupt is disabled Corresponding interrupt is enabled. AT91SAM7A3 Preliminary 144 PID29 PID28 PID27 PID21 PID20 PID19 PID13 PID12 PID11 ...
Page 145
... PID29 PID28 PID27 PID21 PID20 PID19 PID13 PID12 PID11 PID5 PID4 PID3 AT91SAM7A3 Preliminary 26 25 – – – – – – – NIRQ 26 25 PID26 PID25 18 17 PID18 PID17 10 9 PID10 PID9 2 1 PID2 SYS 24 – ...
Page 146
... Register Name: AIC_ICCR Access Type: Write-only 31 30 PID31 PID30 23 22 PID23 PID22 15 14 PID15 PID14 7 6 PID7 PID6 • FIQ, SYS, PID2-PID31: Interrupt Clear effect Clears corresponding interrupt. AT91SAM7A3 Preliminary 146 PID29 PID28 PID27 PID21 PID20 PID19 PID13 PID12 PID11 PID5 ...
Page 147
... PID13 PID12 PID11 PID5 PID4 PID3 – – – – – – – – – – – – AT91SAM7A3 Preliminary 26 25 PID26 PID25 18 17 PID18 PID17 10 9 PID10 PID9 2 1 PID2 SYS 26 25 – – – – – – – – ...
Page 148
... The nIRQ and nFIQ lines are tied to their inactive state. 6042E–ATARM–14-Dec- SIQV SIQV SIQV SIQV – – – – – – – – – – – – AT91SAM7A3 Preliminary – – – – – – – GMSK – 16 – 8 – 0 PROT 148 ...
Page 149
... PID11 PID5 PID4 PID3 PID29 PID28 PID27 PID21 PID20 PID19 PID13 PID12 PID11 PID5 PID4 PID3 AT91SAM7A3 Preliminary 26 25 PID26 PID25 18 17 PID18 PID17 10 9 PID10 PID9 2 1 PID2 SYS 26 25 PID26 PID25 18 17 PID18 PID17 10 9 PID10 PID9 2 1 PID2 ...
Page 150
... PID23 PID22 15 14 PID15 PID14 7 6 PID7 PID6 • SYS, PID2-PID31: Fast Forcing Status 0 = The Fast Forcing feature is disabled on the corresponding interrupt The Fast Forcing feature is enabled on the corresponding interrupt. AT91SAM7A3 Preliminary 150 PID29 PID28 PID27 PID21 PID20 PID19 13 12 ...
Page 151
... However, the Clock Generator registers are named CKGR_. shows the Main Oscillator block diagram. MOSCEN XIN Main Oscillator XOUT OSCOUNT Main SLCK Oscillator Slow Clock Counter Main Clock Frequency Counter AT91SAM7A3 Preliminary MAINCK Main Clock MOSCS MAINF MAINRDY Ω Figure 23-2. The 1 k resistor is only 151 ...
Page 152
... Clock Frequency Register) is set and the counter stops counting. Its value can be read in the MAINF field of CKGR_MCFR and gives the number of Main Clock cycles during 16 periods of Slow Clock, so that the frequency of the crystal connected on the Main Oscillator can be determined. AT91SAM7A3 Preliminary 152 XIN XOUT ...
Page 153
... PLL input frequency, the PLL output frequency and the phase margin. A trade-off has to be found between output signal overshoot and startup time. 6042E–ATARM–14-Dec-06 shows the block diagram of the divider and PLL block. DIV Divider MAINCK SLCK PLLRC GND AT91SAM7A3 Preliminary MUL OUT PLL PLLCK PLLRC PLLCOUNT PLL LOCK Counter PLL Figure 153 ...
Page 154
... The user has to load the number of Slow Clock cycles required to cover the PLL transient time into the PLLCOUNT field. The transient time depends on the PLL filter. The initial state of the PLL and its target frequency can be calculated using a specific tool provided by Atmel. AT91SAM7A3 Preliminary 154 6042E–ATARM–14-Dec-06 ...
Page 155
... This feature is useful when switching from a high-speed clock to a lower one to inform the software when the change is actually done. Figure 24-1. Master Clock Controller MAINCK PLLCK 6042E–ATARM–14-Dec-06 PMC_MCKR PMC_MCKR CSS SLCK Master Clock Prescaler AT91SAM7A3 Preliminary PRES MCK To the Processor Clock Controller (PCK) 155 ...
Page 156
... In order to stop a peripheral recommended that the system software wait until the peripheral has executed its last programmed operation before disabling the clock. This is to avoid data cor- ruption or erroneous behavior of the system. AT91SAM7A3 Preliminary 156 USBDIV USB ...
Page 157
... This measure can be accomplished via the CKGR_MCFR register. Once the MAINRDY field is set in CKGR_MCFR register, the user may read the MAINF field in CKGR_MCFR register. This provides the number of main clock cycles within sixteen slow clock cycles. 3. Setting PLL and divider: 6042E–ATARM–14-Dec-06 write_register(CKGR_MOR,0x00000701) AT91SAM7A3 Preliminary 157 ...
Page 158
... MCKRDY has been enabled in the PMC_IER register. The PMC_MCKR register must not be programmed in a single write operation. The preferred programming sequence for the PMC_MCKR register is as follows: AT91SAM7A3 Preliminary 158 write_register(CKGR_PLLR,0x00040805) 6042E–ATARM–14-Dec-06 ...
Page 159
... CKGR_PLLR, the MCKRDY flag will go low while PLL is unlocked. Once PLL is locked again, LOCK goes high and MCKRDY is set. While PLL is unlocked, the Master Clock selection is automatically changed to Main Clock. For fur- ther information, see Section 24.8.2. ”Clock Switching Waveforms” on page AT91SAM7A3 Preliminary 161. 4 Programmable clocks can be enabled or dis- 159 ...
Page 160
... Depending on the system used, 26 peripheral clocks can be enabled or disabled. The PMC_PCSR provides a clear view as to which peripheral clock is enabled. Note: Code Examples: write_register(PMC_PCER,0x00000110) Peripheral clocks 4 and 8 are enabled. write_register(PMC_PCDR,0x00000010) Peripheral clock 4 is disabled. AT91SAM7A3 Preliminary 160 Each enabled peripheral clock corresponds to Master Clock. 6042E–ATARM–14-Dec-06 ...
Page 161
... Main Clock + 4 x SLCK + PLLCOUNT x SLCK + PLLCOUNT x SLCK 2.5 x PLLx Clock Slow Clock PLL Clock LOCK MCKRDY Master Clock AT91SAM7A3 Preliminary SLCK PLL Clock 3 x PLL Clock + 4 x SLCK + 4 x SLCK + 2.5 x Main Clock 1 x Main Clock 3 x PLL Clock + – ...
Page 162
... Figure 24-4. Switch Master Clock from Main Clock to Slow Clock Write PMC_MCKR Figure 24-5. Change PLL Programming Write CKGR_PLLR AT91SAM7A3 Preliminary 162 Slow Clock Main Clock MCKRDY Master Clock Main Clock PLL Clock LOCK MCKRDY Master Clock Main Clock 6042E–ATARM–14-Dec-06 ...
Page 163
... Figure 24-6. Programmable Clock Output Programming Write PMC_PCKx Write PMC_SCER Write PMC_SCDR 6042E–ATARM–14-Dec-06 PLL Clock PCKRDY PCKx Output PLL Clock is selected AT91SAM7A3 Preliminary PCKx is enabled PCKx is disabled 163 ...
Page 164
... Programmable Clock 0 Register 0x0044 Programmable Clock 1 Register ... ... 0x0060 Interrupt Enable Register 0x0064 Interrupt Disable Register 0x0068 Status Register 0x006C Interrupt Mask Register 0x0070 - 0x007C Reserved AT91SAM7A3 Preliminary 164 Name Access PMC_SCER Write-only PMC_SCDR Write-only PMC _SCSR Read-only – – PMC _PCER Write-only PMC_PCDR ...
Page 165
... PCKx: Programmable Clock x Output Enable effect Enables the corresponding Programmable Clock output. 6042E–ATARM–14-Dec- – – – – – – – – PCK3 – – – AT91SAM7A3 Preliminary 26 25 – – – – PCK2 PCK1 2 1 – – 24 – 16 – 8 PCK0 0 PCK 165 ...
Page 166
... Disables the Processor clock. This is used to enter the processor in Idle Mode. • UDP: USB Device Port Clock Disable effect Disables the 48 MHz clock of the USB Device Port. • PCKx: Programmable Clock x Output Disable effect Disables the corresponding Programmable Clock output. AT91SAM7A3 Preliminary 166 – – ...
Page 167
... The corresponding Programmable Clock output is disabled The corresponding Programmable Clock output is enabled. 6042E–ATARM–14-Dec- – – – – – – – – PCK3 – – – AT91SAM7A3 Preliminary 26 25 – – – – PCK2 PCK1 2 1 – – 24 – 16 – 8 PCK0 0 PCK 167 ...
Page 168
... No effect Enables the corresponding peripheral clock. Note: PID2 to PID31 refer to identifiers as defined in the section “Peripheral Identifiers” in the product datasheet. Note: Programming the control bits of the Peripheral ID that are not implemented has no effect on the behavior of the PMC. AT91SAM7A3 Preliminary 168 PID29 ...
Page 169
... PID2 to PID31 refer to identifiers as defined in the section “Peripheral Identifiers” in the product datasheet. 6042E–ATARM–14-Dec- PID29 PID28 PID27 PID21 PID20 PID19 PID13 PID12 PID11 PID5 PID4 PID3 AT91SAM7A3 Preliminary 26 25 PID26 PID25 18 17 PID18 PID17 10 9 PID10 PID9 2 1 PID2 - 24 PID24 16 PID16 8 PID8 0 - 169 ...
Page 170
... PID15 PID14 7 6 PID7 PID6 • PIDx: Peripheral Clock x Status 0 = The corresponding peripheral clock is disabled The corresponding peripheral clock is enabled. Note: PID2 to PID31 refer to identifiers as defined in the section “Peripheral Identifiers” in the product datasheet. AT91SAM7A3 Preliminary 170 PID29 PID28 PID27 PID21 ...
Page 171
... OSCOUNT: Main Oscillator Start-up Time Specifies the number of Slow Clock cycles multiplied by 8 for the Main Oscillator start-up time. 6042E–ATARM–14-Dec- – – – – – – OSCOUNT – – – AT91SAM7A3 Preliminary 26 25 – – – – – OSCBYPASS 24 – 16 – MOSCEN 171 ...
Page 172
... MAINF: Main Clock Frequency Gives the number of Main Clock cycles within 16 Slow Clock periods. • MAINRDY: Main Clock Ready 0 = MAINF value is not valid or the Main Oscillator is disabled The Main Oscillator has been enabled previously and MAINF value is available. AT91SAM7A3 Preliminary 172 – ...
Page 173
... Divider output is 0 Divider is bypassed Divider output is the selected clock divided by DIV. Divider for USB Clock(s) Divider output is PLL clock output. Divider output is PLL clock output divided by 2. Divider output is PLL clock output divided by 4. Reserved. AT91SAM7A3 Preliminary 26 25 MUL PLLCOUNT ...
Page 174
... Register Name: PMC_MCKR Access Type: Read/Write 31 30 – – – – – – – – • CSS: Master Clock Selection • PRES: Processor Clock Prescaler AT91SAM7A3 Preliminary 174 – – – – – – – – – – PRES CSS PRES ...
Page 175
... PRES Clock Source Selection 0 Slow Clock is selected 1 Main Clock is selected 0 Reserved 1 PLL Clock is selected PRES AT91SAM7A3 Preliminary 26 25 – – – – – CSS Programmable Clock 0 Selected clock 1 Selected clock divided Selected clock divided Selected clock divided Selected clock divided by 16 ...
Page 176
... MOSCS: Main Oscillator Status Interrupt Enable • LOCK: PLL Lock Interrupt Enable • MCKRDY: Master Clock Ready Interrupt Enable • PCKRDYx: Programmable Clock Ready x Interrupt Enable effect Enables the corresponding interrupt. AT91SAM7A3 Preliminary 176 – – – – ...
Page 177
... PCKRDYx: Programmable Clock Ready x Interrupt Disable effect Disables the corresponding interrupt. 6042E–ATARM–14-Dec- – – – – – – – – – – – MCKRDY AT91SAM7A3 Preliminary 26 25 – – – – PCKRDY2 PCKRDY1 2 1 LOCK – 24 – 16 – 8 PCKRDY0 0 MOSCS 177 ...
Page 178
... LOCK: PLL Lock Status 0 = PLL is not locked 1 = PLL is locked. • MCKRDY: Master Clock Status 0 = Master Clock is not ready Master Clock is ready. • PCKRDYx: Programmable Clock Ready Status 0 = Programmable Clock x is not ready Programmable Clock x is ready. AT91SAM7A3 Preliminary 178 – – – 21 ...
Page 179
... PCKRDYx: Programmable Clock Ready x Interrupt Mask 0 = The corresponding interrupt is enabled The corresponding interrupt is disabled. 6042E–ATARM–14-Dec- – – – – – – – – – – – MCKRDY AT91SAM7A3 Preliminary 26 25 – – – – PCKRDY2 PCKRDY1 2 1 LOCK – 24 – 16 – 8 PCKRDY0 0 MOSCS 179 ...
Page 180
... AT91SAM7A3 Preliminary 180 6042E–ATARM–14-Dec-06 ...
Page 181
... DCC under interrupt control. Chip Identifier registers permit recognition of the device and its revision. These registers inform as to the sizes and types of the on-chip memories, as well as the set of embedded peripherals. 6042E–ATARM–14-Dec-06 AT91SAM7A3 Preliminary 181 ...
Page 182
... Power-on Reset Table 25-1. Debug Unit Pin Description Pin Name Description DRXD Debug Receive Data DTXD Debug Transmit Data Figure 25-2. Debug Unit Application Example AT91SAM7A3 Preliminary 182 Peripheral DMA Controller Debug Unit Baud Rate MCK Generator DCC Handler Interrupt Control ...
Page 183
... DBGU_BRGR (Baud Rate Generator Register). If DBGU_BRGR is set to 0, the baud rate clock is disabled and the Debug Unit's UART remains inactive. The maximum allowable baud rate is Master Clock divided by 16. The minimum allowable baud rate is Master Clock divided by (16 x 65536). 6042E–ATARM–14-Dec-06 AT91SAM7A3 Preliminary MCK Baud Rate = -------------------- - × ...
Page 184
... The first sampling point is therefore 24 cycles (1.5-bit periods) after the falling edge of the start bit was detected. Each subsequent bit is sampled 16 cycles (1-bit period) after the previous one. 6042E–ATARM–14-Dec-06 CD MCK 16-bit Counter AT91SAM7A3 Preliminary CD OUT >1 Divide Baud Rate ...
Page 185
... PAR in DBGU_MR. It then compares the result with the received 6042E–ATARM–14-Dec-06 DRXD True Start Detection Baud Rate Clock 0.5 bit 1 bit period period DRXD True Start Detection DRXD DRXD AT91SAM7A3 Preliminary Parity Bit Read DBGU_RHR stop D0 Stop Bit stop RSTSTA 185 ...
Page 186
... Register. One start bit at level 0, then the 8 data bits, from the lowest to the highest bit, one optional parity bit and one stop bit at 1 are consecutively shifted out as shown on the following 6042E–ATARM–14-Dec-06 DRXD PARE DRXD RXRDY FRAME AT91SAM7A3 Preliminary stop Wrong Parity Bit RSTSTA stop Stop Bit RSTSTA Detected at 0 186 ...
Page 187
... Debug Unit user interface from the offset 0x100. The status bits are reported in the Debug Unit status register DBGU_SR and can generate an interrupt. 6042E–ATARM–14-Dec-06 Clock DTXD Start Bit Data 0 Data stop AT91SAM7A3 Preliminary Parity Data 1 Data 1 Data 1 P stop Stop Bit Bit ...
Page 188
... Debug Communication Channel Support The Debug Unit handles the signals COMMRX and COMMTX that come from the Debug Communication Channel of the ARM Processor and are driven by the In-circuit Emulator. 6042E–ATARM–14-Dec-06 AT91SAM7A3 Preliminary Automatic Echo Receiver Disabled Transmitter Local Loopback ...
Page 189
... SRAMSIZ - indicates the size of the embedded SRAM • EPROC - indicates the embedded ARM processor • VERSION - gives the revision of the silicon The second register is device-dependent and reads 0 if the bit EXT is 0. 6042E–ATARM–14-Dec-06 AT91SAM7A3 Preliminary p14, 0, Rd, c1, c0, 0 p14, 0, Rd, c1, c0, 0 189 ...
Page 190
... Baud Rate Generator Register 0x0024 - 0x003C Reserved 0x0040 Chip ID Register 0x0044 Chip ID Extension Register 0x0048 Reserved 0x004C - 0x00FC Reserved 0x0100 - 0x0124 PDC Area 6042E–ATARM–14-Dec-06 AT91SAM7A3 Preliminary Name Access DBGU_CR Write-only DBGU_MR Read/Write DBGU_IER Write-only DBGU_IDR Write-only DBGU_IMR Read-only DBGU_SR ...
Page 191
... Resets the status bits PARE, FRAME and OVRE in the DBGU_SR. 6042E–ATARM–14-Dec- – – – – – – – – – RXDIS RXEN RSTTX AT91SAM7A3 Preliminary 26 25 – – – – – – – RSTRX 24 – 16 – 8 RSTSTA 0 – 191 ...
Page 192
... Parity Type 0 Even parity 1 Odd parity 0 Space: parity forced Mark: parity forced parity Mode Description Normal Mode Automatic Echo Local Loopback Remote Loopback AT91SAM7A3 Preliminary – – – – – – PAR – – – 24 – ...
Page 193
... COMMRX: Enable COMMRX (from ARM) Interrupt effect Enables the corresponding interrupt. 6042E–ATARM–14-Dec- – – – – – – – RXBUFF TXBUFE OVRE ENDTX ENDRX AT91SAM7A3 Preliminary 26 25 – – – – – TXEMPTY 2 1 – TXRDY 24 – 16 – 8 – 0 RXRDY 193 ...
Page 194
... COMMRX: Disable COMMRX (from ARM) Interrupt effect Disables the corresponding interrupt. 6042E–ATARM–14-Dec- – – – – – – – RXBUFF TXBUFE OVRE ENDTX ENDRX AT91SAM7A3 Preliminary 26 25 – – – – – TXEMPTY 2 1 – TXRDY 24 – 16 – 8 – 0 RXRDY 194 ...
Page 195
... COMMRX: Mask COMMRX Interrupt 0 = The corresponding interrupt is disabled The corresponding interrupt is enabled. 6042E–ATARM–14-Dec- – – – – – – – RXBUFF TXBUFE OVRE ENDTX ENDRX AT91SAM7A3 Preliminary 26 25 – – – – – TXEMPTY 2 1 – TXRDY 24 – 16 – 8 – 0 RXRDY 195 ...
Page 196
... The buffer full signal from the receiver PDC channel is active. 6042E–ATARM–14-Dec- – – – – – – – RXBUFF TXBUFE OVRE ENDTX ENDRX AT91SAM7A3 Preliminary 26 25 – – – – – TXEMPTY 2 1 – TXRDY 24 – 16 – 8 – 0 RXRDY 196 ...
Page 197
... COMMTX: Debug Communication Channel Write Status 0 = COMMTX from the ARM processor is inactive COMMTX from the ARM processor is active. • COMMRX: Debug Communication Channel Read Status 0 = COMMRX from the ARM processor is inactive COMMRX from the ARM processor is active. 6042E–ATARM–14-Dec-06 AT91SAM7A3 Preliminary 197 ...
Page 198
... RXCHR: Received Character Last received character if RXRDY is set. 6042E–ATARM–14-Dec- – – – – – – – – – RXCHR AT91SAM7A3 Preliminary 26 25 – – – – – – – 16 – 8 – 0 198 ...
Page 199
... TXCHR: Character to be Transmitted Next character to be transmitted after the current character if TXRDY is not set. 6042E–ATARM–14-Dec- – – – – – – – – – TXCHR AT91SAM7A3 Preliminary 26 25 – – – – – – – 16 – 8 – 0 199 ...
Page 200
... Name: DBGU_BRGR Access Type: Read/Write 31 30 – – – – • CD: Clock Divisor CD Baud Rate Clock 0 Disabled 1 MCK 2 to 65535 MCK / (CD x 16) 6042E–ATARM–14-Dec- – – – – – – AT91SAM7A3 Preliminary 26 25 – – – – – 16 – 200 ...