LPC3131FET180,551 NXP Semiconductors, LPC3131FET180,551 Datasheet - Page 45

• Manufacturer Part Number: LPC3131FET180,551
• Description: IC ARM9 MCU 180MHZ 180-TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC3000r

Specifications of LPC3131FET180,551

• Package / Case: 180-TFBGA
• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, PWM, WDT
• Program Memory Type: ROMless
• Ram Size: 192K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC31
• Core: ARM926EJ-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 192 KB
• Interface Type: I2C/I2S/UART/USB
• Maximum Clock Frequency: 180 MHz
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, KSK-LPC3131-PL
• Development Tools By Supplier: OM11028
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 4-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 568-4850 - KIT EVAL FOR LPC313X568-4062 - DEBUGGER J-LINK JTAG568-4061 - DEBUGGER U-LINK2 JTAG FOR NXP
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4697; 935288014551; LPC3131FET180-S

NXP Semiconductors
Table 14.
[1]
[2]
[3]
[4]
[5]
[6]
LPC3130_3131
Preliminary data sheet
Symbol
Internal SRAM based system (operating frequency 180 MHz (core)/ 90 MHz (bus)); normal mode power; without
dynamic clock scaling; MMU off
I
P
DD
12 Mhz oscillator running; PLLs off; SYS_BASE and AHB_APB0_BASE Base domain clocks are enabled, driven by 12 Mhz oscillator;
all peripherals off; SUP4 buffers set to input w/PD; SUP8 and SUP3 buffers set to input w/repeater. Shutting off the 12 Mhz osc will
reduce power to 1.4 mW (requires a RSTIN_N to run again).
Running Linux with 100% load; all peripherals on; instruction and data caches on; MMU on.
Dynamic clock scaling active; hardware will automatically switch the SYSBASE clocks to a slow clock (180 / 64 = 2.81 MHz) during
times of bus inactivity. ARM926 and NAND flash clocks are not scaled for this test.
Running Linux idle at prompt; all peripherals on; instruction and data caches on; MMU on.
Running Dhrystone test (600 k/sec); UART and timers enabled; instruction and data caches on; MMU on.
Running Dhrystone test (121.83 k/sec); UART and timers enabled; instruction and data caches off; MMU off.
Parameter
Supply current
Power dissipation
Power consumption
Conditions
core; VDDI = 1.2 V
all other SUP1 supplies: VDDA12 = 1.2 V;
USB_VDDA12_PL = 1.2 V
VDDE_IOA = 1.8 V
VDDE_IOB = 1.8 V
VDDE_IOC = 3.3 V
ADC10B_VDDA33 = 3.3 V
USB_VDDA33 = 3.3 V
USB_VDDA_DRV = 3.3 V
Total for supply domains SUP1, SUP3, SUP4,
SUP8
…continued
[6]
All information provided in this document is subject to legal disclaimers.
Rev. 1.04 — 27 May 2010
Low-cost, low-power ARM926EJ-S microcontrollers
LPC3130/3131
Min
-
-
-
-
-
-
-
-
-
Typ
26.3
1.57
1
0.038
0.068
0.0002
1.59
0.89
43.7
© NXP B.V. 2010. All rights reserved.
Max
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-
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-
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-
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-
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Unit
mA
mA
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mA
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mA
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mA
mW