IC ARM CORTEX MCU 256K 100-LQFP

LPC1765FBD100,551

Manufacturer Part NumberLPC1765FBD100,551
DescriptionIC ARM CORTEX MCU 256K 100-LQFP
ManufacturerNXP Semiconductors
SeriesLPC17xx
LPC1765FBD100,551 datasheets
 


Specifications of LPC1765FBD100,551

Program Memory TypeFLASHProgram Memory Size256KB (256K x 8)
Package / Case100-LQFPCore ProcessorARM® Cortex-M3™
Core Size32-BitSpeed100MHz
ConnectivityCAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTGPeripheralsBrown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o70Ram Size64K x 8
Voltage - Supply (vcc/vdd)2.4 V ~ 3.6 VData ConvertersA/D 8x12b, D/A 1x10b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Processor SeriesLPC17CoreARM Cortex M3
Data Bus Width32 bitData Ram Size64 KB
Interface TypeCAN, I2C, SPI, UARTMaximum Clock Frequency100 MHz
Number Of Programmable I/os70Number Of Timers3
Operating Supply Voltage3.3 VMaximum Operating Temperature+ 85 C
Mounting StyleSMD/SMT3rd Party Development ToolsMDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
Development Tools By SupplierOM11032, OM11033, OM11034, OM11035, OM11043Minimum Operating Temperature- 40 C
On-chip Adc12 bit, 8 ChannelOn-chip Dac10 bit
Package100LQFPDevice CoreARM Cortex M3
Family NameLPC17xxMaximum Speed100 MHz
Cpu FamilyLPC17xxDevice Core Size32b
Frequency (max)100MHzTotal Internal Ram Size64KB
# I/os (max)70Number Of Timers - General Purpose4
Operating Supply Voltage (typ)3.3VOperating Supply Voltage (max)3.6V
Operating Supply Voltage (min)2.4VInstruction Set ArchitectureRISC
Operating Temp Range-40C to 85COperating Temperature ClassificationIndustrial
MountingSurface MountPin Count100
Package TypeLQFPLead Free Status / RoHS StatusLead free / RoHS Compliant
For Use With622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2KEeprom Size-
Other names568-4794
935287918551
  
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LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller; up to 512 kB flash and
64 kB SRAM with Ethernet, USB 2.0 Host/Device/OTG, CAN
Rev. 6.01 — 11 March 2011
1. General description
The LPC1769/68/67/66/65/64/63 are ARM Cortex-M3 based microcontrollers for
embedded applications featuring a high level of integration and low power consumption.
The ARM Cortex-M3 is a next generation core that offers system enhancements such as
enhanced debug features and a higher level of support block integration.
The LPC1768/67/66/65/64/63 operate at CPU frequencies of up to 100 MHz. The
LPC1769 operates at CPU frequencies of up to 120 MHz. The ARM Cortex-M3 CPU
incorporates a 3-stage pipeline and uses a Harvard architecture with separate local
instruction and data buses as well as a third bus for peripherals. The ARM Cortex-M3
CPU also includes an internal prefetch unit that supports speculative branching.
The peripheral complement of the LPC1769/68/67/66/65/64/63 includes up to 512 kB of
flash memory, up to 64 kB of data memory, Ethernet MAC, USB Device/Host/OTG
interface, 8-channel general purpose DMA controller, 4 UARTs, 2 CAN channels, 2 SSP
controllers, SPI interface, 3 I
8-channel 12-bit ADC, 10-bit DAC, motor control PWM, Quadrature Encoder interface,
four general purpose timers, 6-output general purpose PWM, ultra-low power Real-Time
Clock (RTC) with separate battery supply, and up to 70 general purpose I/O pins.
The LPC1769/68/67/66/65/64/63 are pin-compatible to the 100-pin LPC236x
ARM7-based microcontroller series.
2. Features and benefits
ARM Cortex-M3 processor, running at frequencies of up to 100 MHz
(LPC1768/67/66/65/64/63) or of up to 120 MHz (LPC1769). A Memory Protection Unit
(MPU) supporting eight regions is included.
ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).
Up to 512 kB on-chip flash programming memory. Enhanced flash memory accelerator
enables high-speed 120 MHz operation with zero wait states.
In-System Programming (ISP) and In-Application Programming (IAP) via on-chip
bootloader software.
On-chip SRAM includes:
32/16 kB of SRAM on the CPU with local code/data bus for high-performance CPU
access.
2
C-bus interfaces, 2-input plus 2-output I
Product data sheet
2
S-bus interface,

LPC1765FBD100,551 Summary of contents

  • Page 1

    LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 512 kB flash and 64 kB SRAM with Ethernet, USB 2.0 Host/Device/OTG, CAN Rev. 6.01 — 11 March 2011 1. General description The LPC1769/68/67/66/65/64/63 are ARM Cortex-M3 based microcontrollers for embedded applications featuring ...

  • Page 2

    ... NXP Semiconductors Two/one 16 kB SRAM blocks with separate access paths for higher throughput. These SRAM blocks may be used for Ethernet, USB, and DMA memory, as well as for general purpose CPU instruction and data storage. Eight channel General Purpose DMA controller (GPDMA) on the AHB multilayer ...

  • Page 3

    ... NXP Semiconductors Quadrature encoder interface that can monitor one external quadrature encoder. One standard PWM/timer block with external count input. RTC with a separate power domain and dedicated RTC oscillator. The RTC block includes 20 bytes of battery-powered backup registers. WatchDog Timer (WDT). The WDT can be clocked from the internal RC oscillator, the RTC oscillator, or the APB clock ...

  • Page 4

    ... NXP Semiconductors 3. Applications eMetering Lighting Industrial networking 4. Ordering information Table 1. Ordering information Type number Package Name Description LPC1769FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14 × 14 × 1.4 mm LPC1768FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14 × 14 × 1.4 mm ...

  • Page 5

    ... NXP Semiconductors 5. Block diagram debug JTAG port interface TEST/DEBUG INTERFACE ARM CORTEX-M3 I-code D-code bus bus slave P0 to HIGH-SPEED P4 GPIO APB slave group 0 SCK1 SSEL1 SSP1 MISO1 MOSI1 RXD0/TXD0 UART0/1 8 × UART1 RD1/2 (1) CAN1/2 TD1/2 SCL0/1 I2C0/1 SDA0/1 SCK/SSEL SPI0 MOSI/MISO 2 × ...

  • Page 6

    ... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 2. Pin configuration LQFP100 package Fig 3. Pin configuration TFBGA100 package Table 3. Pin allocation table Pin Symbol Pin Symbol Row A 1 TDO/SWO 2 P0[3]/RXD0/AD0[6] 5 P1[10]/ENET_RXD1 6 P1[16]/ENET_MDC 9 P0[7]/I2STX_CLK/ 10 P0[9]/I2STX_SDA/ SCK1/MAT2[1] MOSI1/MAT2[3] Row B 1 TMS/SWDIO ...

  • Page 7

    ... NXP Semiconductors Table 3. Pin allocation table …continued Pin Symbol Pin Symbol 5 P1[9]/ENET_RXD0 6 P1[17]/ ENET_MDIO 9 P2[0]/PWM1[1]/TXD1 10 P2[1]/PWM1[2]/RXD1 Row C 1 TCK/SWDCLK 2 TRST 5 P1[8]/ENET_CRS 6 P1[15]/ ENET_REF_CLK DD(3V3) Row D 1 P0[24]/AD0[1]/ 2 P0[25]/AD0[2]/ I2SRX_WS/CAP3[1] I2SRX_SDA/TXD3 5 P1[0]/ENET_TXD0 6 P1[14]/ENET_RX_ER ...

  • Page 8

    ... NXP Semiconductors Table 3. Pin allocation table …continued Pin Symbol Pin Symbol Row J 1 P0[28]/SCL0/ 2 P0[27]/SDA0/ USB_SCL USB_SDA 5 P1[22]/MCOB0 USB_PWRD/ MAT1[0] 9 P2[13]/EINT3/ 10 P2[10]/EINT0/NMI I2STX_SDA Row K 1 P3[26]/STCLK DD(3V3) MAT0[1]/PWM1[3] 5 P1[23]/MCI1/ 6 P1[26]/MCOB1/ PWM1[4]/MISO0 ...

  • Page 9

    ... NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [1] [1] P0[4 I2SRX_CLK/ RD2/CAP2[0] P0[5]/ 80 [1] D7 [1] I2SRX_WS/ TD2/CAP2[1] [1] [1] P0[6 I2SRX_SDA/ SSEL1/MAT2[0] [1] [1] P0[7 I2STX_CLK/ SCK1/MAT2[1] [1] [1] P0[8 I2STX_WS/ MISO1/MAT2[2] [1] [1] P0[9]/ 76 A10 I2STX_SDA/ MOSI1/MAT2[3] P0[10]/TXD2/ 48 [1] H7 [1] SDA2/MAT3[0] [1] [1] ...

  • Page 10

    ... NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [1] [1] P0[15]/TXD1/ 62 F10 SCK0/SCK [1] [1] P0[16]/RXD1 SSEL0/SSEL P0[17]/CTS1/ 61 [1] F9 [1] MISO0/MISO [1] [1] P0[18]/DCD1 MOSI0/MOSI P0[19]/DSR1/ 59 [1] G10 [1] SDA1 P0[20]/DTR1/SCL1 58 [1] G9 [1] P0[21]/RI1/RD1 57 [1] G8 [1] [1] [1] ...

  • Page 11

    ... NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [2] [2] P0[24]/AD0[1 I2SRX_WS/ CAP3[1] P0[25]/AD0[2]/ 7 [2] D2 [2] I2SRX_SDA/ TXD3 [3] [3] P0[26]/AD0[3 AOUT/RXD3 P0[27]/SDA0/ 25 [4] J2 [4] USB_SDA P0[28]/SCL0/ 24 [4] J1 [4] USB_SCL [5] [5] P0[29]/USB_D [5] [5] P0[30]/USB_D− ...

  • Page 12

    ... NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [1] [1] P1[9 ENET_RXD0 [1] [1] P1[10 ENET_RXD1 [1] [1] P1[14 ENET_RX_ER P1[15]/ 88 [1] C6 [1] ENET_REF_CLK [1] [1] P1[16 ENET_MDC [1] [1] P1[17 ENET_MDIO [1] [1] P1[18 USB_UP_LED/ PWM1[1]/ CAP1[0] [1] [1] P1[19]/MCOA0 USB_PPWR/ CAP1[1] P1[20]/MCI0/ 34 [1] ...

  • Page 13

    ... NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [1] [1] P1[23]/MCI1 PWM1[4]/MISO0 P1[24]/MCI2/ 38 [1] H5 [1] PWM1[5]/MOSI0 [1] [1] P1[25]/MCOA1 MAT1[1] P1[26]/MCOB1/ 40 [1] K6 [1] PWM1[6]/CAP0[0] [1] [1] P1[27]/CLKOUT 43 K7 /USB_OVRCR/ CAP0[1] P1[28]/MCOA2/ 44 [1] J7 [1] PCAP1[0]/ ...

  • Page 14

    ... NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [1] [1] P2[0]/PWM1[1 TXD1 P2[1]/PWM1[2]/ 74 [1] B10 [1] RXD1 P2[2]/PWM1[3]/ 73 [1] D8 [1] CTS1/ TRACEDATA[3] [1] [1] P2[3]/PWM1[4 DCD1/ TRACEDATA[2] [1] [1] P2[4]/PWM1[5 DSR1/ TRACEDATA[1] P2[5]/PWM1[6]/ 68 [1] D10 [1] DTR1/ TRACEDATA[0] [1] [1] ...

  • Page 15

    ... NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [6] [6] P2[10]/EINT0/NMI 53 J10 [6] [6] P2[11]/EINT1 I2STX_CLK [6] [6] P2[12]/EINT2/ 51 K10 I2STX_WS [6] [6] P2[13]/EINT3 I2STX_SDA P3[0] to P3[31] [1] [1] P3[25]/MAT0[0 PWM1[2] P3[26]/STCLK/ 26 [1] K1 [1] MAT0[1]/PWM1[3] P4[0] to P4[31] [1] [1] ...

  • Page 16

    ... NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [1][8] [1][8] TDI 2 C3 TMS/SWDIO 3 [1][8] B1 [1][8] TRST 4 [1][8] C2 [1][8] [1][7] [1][7] TCK/SWDCLK 5 C1 RTCK 100 [1][7] B2 [1][7] RSTOUT 14 - [9] [9] RESET 17 F3 XTAL1 22 [10][11] H2 [10][11] [10][11] [10][11] XTAL2 23 G3 ...

  • Page 17

    ... NXP Semiconductors [4] Open-drain 5 V tolerant digital I/O pad, compatible with I output functionality. When power is switched off, this pin connected to the I Open-drain configuration applies to all functions on this pin. [5] Pad provides digital I/O and USB functions designed in accordance with the USB specification, revision 2.0 (Full-speed and Low-speed mode only) ...

  • Page 18

    ... NXP Semiconductors 7. Functional description 7.1 Architectural overview Remark: In the following, the notation LPC17xx refers to all parts: LPC1769/68/67/66/65/64/63. The ARM Cortex-M3 includes three AHB-Lite buses: the system bus, the I-code bus, and the D-code bus (see system bus and are used similarly to TCM interfaces: one bus dedicated for instruction fetch (I-code) and one bus for data access (D-code) ...

  • Page 19

    ... NXP Semiconductors The MPU allows separating processing tasks by disallowing access to each other's data, disabling access to memory regions, allowing memory regions to be defined as read-only and detecting unexpected memory accesses that could potentially break the system. The MPU separates the memory into distinct regions and implements protection by preventing disallowed accesses ...

  • Page 20

    APB1 peripherals 0x4010 0000 31 system control 0x400F C000 reserved 0x400C 0000 15 QEI 0x400B C000 14 motor control PWM 0x400B 8000 ...

  • Page 21

    ... NXP Semiconductors 7.7 Nested Vectored Interrupt Controller (NVIC) The NVIC is an integral part of the Cortex-M3. The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts. 7.7.1 Features Controls system exceptions and peripheral interrupts • In the LPC17xx, the NVIC supports 33 vectored interrupts • ...

  • Page 22

    ... NXP Semiconductors 7.9.1 Features Eight DMA channels. Each channel can support an unidirectional transfer. • 16 DMA request lines. • Single DMA and burst DMA request signals. Each peripheral connected to the DMA • Controller can assert either a burst DMA request or a single DMA request. The DMA burst size is set by programming the DMA Controller ...

  • Page 23

    ... NXP Semiconductors Additionally, any pin on Port 0 and Port 2 (total of 42 pins) providing a digital function can be programmed to generate an interrupt on a rising edge, a falling edge, or both. The edge detection is asynchronous may operate when clocks are not present such as during Power-down mode. Each enabled interrupt can be used to wake up the chip from Power-down mode ...

  • Page 24

    ... NXP Semiconductors Enhanced Ethernet features: • – Receive filtering. – Multicast and broadcast frame support for both transmit and receive. – Optional automatic Frame Check Sequence (FCS) insertion with Cyclic Redundancy Check (CRC) for transmit. – Selectable automatic transmit frame padding. ...

  • Page 25

    ... NXP Semiconductors Endpoint Maximum packet size selection (up to USB maximum specification) by • software at run time. Supports SoftConnect and GoodLink features. • While USB is in the Suspend mode, the part can enter one of the reduced power • modes and wake up on USB activity. ...

  • Page 26

    ... NXP Semiconductors 7.13.1 Features Two CAN controllers and buses. • Data rates to 1 Mbit/s on each bus. • 32-bit register and RAM access. • Compatible with CAN specification 2.0B, ISO 11898-1. • Global Acceptance Filter recognizes standard (11-bit) and extended-frame (29-bit) • ...

  • Page 27

    ... NXP Semiconductors 7.16 UARTs The LPC17xx each contain four UARTs. In addition to standard transmit and receive data lines, UART1 also provides a full modem control handshake interface and support for RS-485/9-bit mode allowing both software address detection and automatic address detection using 9-bit mode. ...

  • Page 28

    ... NXP Semiconductors data transfer. The SSP supports full duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the slave and from the slave to the master. In practice, often only one of these data flows carries meaningful data. 7.18.1 Features Maximum SSP speed of 50 Mbit/s (master Mbit/s (slave) • ...

  • Page 29

    ... NXP Semiconductors 2 7.20 I S-bus serial I/O controllers Remark: The I2S-bus interface is available on parts LPC1769/68/67/66/65/63. See Table 2. 2 The I S-bus provides a standard communication interface for digital audio applications. The I S-bus specification defines a 3-wire serial bus using one data line, one clock line, 2 and one word select signal ...

  • Page 30

    ... NXP Semiconductors Up to four external outputs corresponding to match registers, with the following • capabilities: – Set LOW on match. – Set HIGH on match. – Toggle on match. – Do nothing on match two match registers can be used to generate timed DMA requests. • 7.22 Pulse width modulator The PWM is based on the standard Timer block and inherits all of its features, although only the PWM function is pinned out on the LPC17xx ...

  • Page 31

    ... NXP Semiconductors Supports single edge controlled and/or double edge controlled PWM outputs. Single • edge controlled PWM outputs all go high at the beginning of each cycle unless the output is a constant low. Double edge controlled PWM outputs can have either edge occur at any position within a cycle. This allows for both positive going and negative going pulses ...

  • Page 32

    ... NXP Semiconductors Digital filter with programmable delays for encoder input signals. • Can accept decoded signal inputs (clk and direction). • Connected to APB. • 7.25 Repetitive Interrupt (RI) timer The repetitive interrupt timer provides a free-running 32-bit counter which is compared to a selectable value, generating an interrupt when a match occurs. Any bits of the timer/compare can be masked such that they do not contribute to the match detection ...

  • Page 33

    ... NXP Semiconductors conditions. It also provides the ability to run the WDT from an entirely internal source that is not dependent on an external crystal and its associated components and wiring for increased reliability. Includes lock/safe feature. • 7.28 RTC and backup registers The RTC is a set of counters for measuring time when system power is on, and optionally when it is off. The RTC on the LPC17xx is designed to have extremely low power consumption, i.e. less than 1 μ ...

  • Page 34

    ... NXP Semiconductors See Figure 5 LPC17xx MAIN OSCILLATOR system clock select (CLKSRCSEL) INTERNAL RC OSCILLATOR 32 kHz RTC rtclk = 1Hz OSCILLATOR Fig 5. LPC17xx clocking generation block diagram 7.29.1.1 Internal RC oscillator The IRC may be used as the clock source for the WDT, and/or as the clock that drives the PLL and subsequently the CPU ...

  • Page 35

    ... NXP Semiconductors 7.29.2 Main PLL (PLL0) The PLL0 accepts an input clock frequency in the range of 32 kHz to 25 MHz. The input frequency is multiplied high frequency, then divided down to provide the actual clock used by the CPU and/or the USB block. The PLL0 input, in the range of 32 kHz to 25 MHz, may initially be divided down by a value ‘ ...

  • Page 36

    ... NXP Semiconductors whenever any of the aforementioned functions are turned off for any reason. Since the oscillator and other functions are turned off during Power-down mode, any wake-up of the processor from Power-down mode makes use of the wake-up timer. The Wake-up Timer monitors the crystal oscillator to check whether it is safe to begin code execution ...

  • Page 37

    ... NXP Semiconductors The Deep-sleep mode can be terminated and normal operation resumed by either a Reset or certain specific interrupts that are able to function without clocks. Since all dynamic operation of the chip is suspended, Deep-sleep mode reduces chip power consumption to a very low value. Power to the flash memory is left on in Deep-sleep mode, allowing a very quick wake-up ...

  • Page 38

    ... NXP Semiconductors 7.29.8 Power domains The LPC17xx provide two independent power domains that allow the bulk of the device to have power removed while maintaining operation of the RTC and the backup Registers. On the LPC17xx, I/O pads are powered by the 3 DD(REG)(3V3) CPU and most of the peripherals. ...

  • Page 39

    ... NXP Semiconductors V Fig 6. Power distribution 7.30 System control 7.30.1 Reset Reset has four sources on the LPC17xx: the RESET pin, the Watchdog reset, power-on reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt trigger input pin. Assertion of chip Reset by any source, once the operating voltage attains ...

  • Page 40

    ... NXP Semiconductors 7.30.2 Brownout detection The LPC17xx include 2-stage monitoring of the voltage on the V voltage falls below 2.2 V, the BOD asserts an interrupt signal to the Vectored Interrupt Controller. This signal can be enabled for interrupt in the Interrupt Enable Register in the NVIC in order to cause a CPU interrupt; if not, software can monitor the signal by reading a dedicated status register ...

  • Page 41

    ... NXP Semiconductors 7.30.5 AHB multilayer matrix The LPC17xx use an AHB multilayer matrix. This matrix connects the instruction (I-code) and data (D-code) CPU buses of the ARM Cortex-M3 to the flash memory, the main (32 kB) static RAM, and the Boot ROM. The GPDMA can also access all of these memories ...

  • Page 42

    ... NXP Semiconductors 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage (3.3 V) DD(3V3) V regulator supply voltage (3.3 V) DD(REG)(3V3) V analog 3.3 V pad supply voltage DDA V input voltage on pin VBAT i(VBAT) V input voltage on pin VREFP ...

  • Page 43

    ... NXP Semiconductors 9. Thermal characteristics The average chip junction temperature, T equation amb T = ambient temperature (°C), • amb R = the package junction-to-ambient thermal resistance (°C/W) • th(j- sum of internal and I/O power dissipation • D The internal power dissipation is the product of I the I/O pins is often small and many times can be negligible. However it can be significant in some applications ...

  • Page 44

    ... NXP Semiconductors 10. Static characteristics Table 7. Static characteristics − ° ° +85 C, unless otherwise specified. amb Symbol Parameter Supply pins V supply voltage (3.3 V) DD(3V3) V regulator supply voltage DD(REG)(3V3) (3 analog 3.3 V pad supply DDA voltage V input voltage on pin i(VBAT) VBAT V input voltage on pin ...

  • Page 45

    ... NXP Semiconductors Table 7. Static characteristics …continued − ° ° +85 C, unless otherwise specified. amb Symbol Parameter I ADC supply current DD(ADC) I ADC input current I(ADC) Standard port pins, RESET, RTCK I LOW-level input current HIGH-level input IH current I OFF-state output OZ current V input voltage I V output voltage ...

  • Page 46

    ... NXP Semiconductors Table 7. Static characteristics …continued − ° ° +85 C, unless otherwise specified. amb Symbol Parameter 2 I C-bus pins (P0[27] and P0[28]) V HIGH-level input IH voltage V LOW-level input voltage IL V hysteresis voltage hys V LOW-level output OL voltage I input leakage current LI Oscillator pins V input voltage on pin ...

  • Page 47

    ... NXP Semiconductors [5] Applies to LPC1768/67/66/65/64/63. [6] Applies to LPC1769 only. [7] IRC running at 4 MHz; main oscillator and PLL disabled; PCLK = [8] BOD disabled. [9] On pin 530 nA. V DD(REG)(3V3) BAT DD(REG)(3V3) [10] On pin VBAT 630 nA; V DD(REG)(3V3) [11] On pin VBAT 3 °C. BAT amb [12] All internal pull-ups disabled ...

  • Page 48

    ... NXP Semiconductors 120 I DD(Reg)(3V3) (μ −40 Conditions: V Fig 8. Power-down mode: Typical regulator supply current I temperature 1.8 I BAT) (μA) 1.4 1.0 0.6 -40 Conditions: V Fig 9. Deep power-down mode: Typical battery supply current I LPC1769_68_67_66_65_64_63 Product data sheet LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller − 3.3 V ...

  • Page 49

    ... NXP Semiconductors 2.0 I DD(REG)(3V3) (µA) 1.6 1.2 0.8 0.4 0 Conditions: V Fig 10. Deep power-down mode: Typical regulator supply current I supply current I LPC1769_68_67_66_65_64_63 Product data sheet LPC1769/68/67/66/65/64/63 /I BAT - 3.0 V; RTC running. BAT DD(REG)(3V3) versus temperature BAT All information provided in this document is subject to legal disclaimers. ...

  • Page 50

    ... NXP Semiconductors 10.2 Peripheral power consumption The supply current per peripheral is measured as the difference in supply current between the peripheral block enabled and the peripheral block disabled in the PCONP register. All other blocks are disabled and no code is executed. Measured on a typical sample ° ...

  • Page 51

    ... NXP Semiconductors 10.3 Electrical pin characteristics 3 (V) 3.2 2.8 2.4 2.0 0 Conditions: V Fig 11. Typical HIGH-level output voltage (mA Conditions: V Fig 12. Typical LOW-level output current I LPC1769_68_67_66_65_64_63 Product data sheet LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller °C 25 °C −40 ° 3.3 V; standard port pins. DD(REG)(3V3) ...

  • Page 52

    ... NXP Semiconductors (μA) −10 −30 −50 −70 0 Conditions: V Fig 13. Typical pull-up current (μ −10 0 Conditions: V Fig 14. Typical pull-down current I LPC1769_68_67_66_65_64_63 Product data sheet LPC1769/68/67/66/65/64/ °C 25 °C −40 ° 3.3 V; standard port pins. DD(REG)(3V3) DD(3V3) versus input voltage °C 25 °C −40 °C ...

  • Page 53

    ... NXP Semiconductors 11. Dynamic characteristics 11.1 Flash memory Table 9. Flash characteristics − ° ° +85 C, unless otherwise specified. amb Symbol Parameter N endurance endu t retention time ret t erase time er t programming time prog [1] Number of program/erase cycles. [2] Programming times are given for writing 256 bytes from RAM to the flash. Data must be written to the flash in blocks of 256 bytes. ...

  • Page 54

    ... NXP Semiconductors 11.3 Internal oscillators Table 11. Dynamic characteristic: internal oscillators − ° ° ≤ + amb DD(3V3) Symbol Parameter f internal RC oscillator frequency osc(RC) f RTC input frequency i(RTC) [1] Parameters are valid over operating temperature range unless otherwise specified. [2] Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply voltages. ...

  • Page 55

    ... NXP Semiconductors 2 11.5 I C-bus Table 13. Dynamic characteristic: I − ° +85 amb Symbol f SCL LOW t HIGH t HD;DAT t SU;DAT [1] See the I 2 C-bus specification UM10204 for details. [2] Parameters are valid over operating temperature range unless otherwise specified. [ the data hold time that is measured from the falling edge of SCL; applies to data in transmission HD ...

  • Page 56

    ... NXP Semiconductors SDA HD;DAT SCL SCL 2 Fig 17. I C-bus pins clock timing 2 11.6 I S-bus interface Remark: The I2S-bus interface is available on parts LPC1769/68/67/66/65/63. See Table 2. Table 14. Dynamic characteristics: I − ° ° +85 C. amb Symbol Parameter common to input and output t rise time r t fall time ...

  • Page 57

    ... NXP Semiconductors I2STX_CLK I2STX_SDA I2STX_WS 2 Fig 18. I S-bus timing (output) I2SRX_CLK I2SRX_SDA I2SRX_WS 2 Fig 19. I S-bus timing (input) LPC1769_68_67_66_65_64_63 Product data sheet LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller T cy(clk v(Q) t v(Q) T cy(clk su(D) t su(D) All information provided in this document is subject to legal disclaimers. ...

  • Page 58

    ... NXP Semiconductors 11.7 SSP interface Table 15. Dynamic characteristic: SSP interface ° over specified ranges. amb DD(3V3) Symbol Parameter SSP interface t SPI_MISO set-up time su(SPI_MISO) [1] The peripheral clock for SSP is PCLK = CCLK = 20 MHz. shifting edges SCK MOSI MISO Fig 20. MISO line set-up time in SSP Master mode ...

  • Page 59

    ... NXP Semiconductors 11.8 USB interface Remark: The USB controller is available as a device/Host/OTG controller on parts LPC1769/68/66/65 and as device-only controller on part LPC1764. Table 16. Dynamic characteristics: USB pins (full-speed) Ω pF 1 DD(3V3) Symbol Parameter t rise time r t fall time f t differential rise and fall time ...

  • Page 60

    ... NXP Semiconductors 11.9 SPI Table 17. Dynamic characteristics of SPI pins − ° +85 amb Symbol Parameter T PCLK cycle time cy(PCLK) T SPI cycle time SPICYC t SPICLK HIGH time SPICLKH t SPICLK LOW time SPICLKL SPI master t SPI data set-up time SPIDSU t SPI data hold time ...

  • Page 61

    ... NXP Semiconductors Fig 23. SPI master timing (CPHA = 0) SCK (CPOL = 0) SCK (CPOL = 1) Fig 24. SPI slave timing (CPHA = 1) LPC1769_68_67_66_65_64_63 Product data sheet LPC1769/68/67/66/65/64/63 T SPICYC SCK (CPOL = 0) SCK (CPOL = 1) t SPIQV DATA VALID MOSI t DATA VALID MISO T SPICYC MOSI DATA VALID t SPIQV MISO DATA VALID All information provided in this document is subject to legal disclaimers. Rev. 6.01 — ...

  • Page 62

    ... NXP Semiconductors Fig 25. SPI slave timing (CPHA = 0) 12. ADC electrical characteristics Table 18. ADC characteristics (full resolution) − ° 2 3 +85 DDA amb Symbol Parameter V analog input voltage IA C analog input capacitance ia E differential linearity error D E integral non-linearity L(adj) E offset error O E gain error ...

  • Page 63

    ... NXP Semiconductors Table 19. ADC characteristics (lower resolution) − ° ° +85 C unless otherwise specified; 12-bit ADC used as 10-bit resolution ADC. amb Symbol Parameter E differential linearity error D E integral non-linearity L(adj) E offset error O E gain error G f ADC clock frequency clk(ADC) f ADC conversion frequency 3 V ≤ V ...

  • Page 64

    ... NXP Semiconductors 4095 4094 4093 4092 4091 4090 7 code out offset error E O (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error ( (4) Integral non-linearity (E ). L(adj) (5) Center of a step of the actual transfer curve. Fig 26. 12-bit ADC characteristics LPC1769_68_67_66_65_64_63 Product data sheet ...

  • Page 65

    ... NXP Semiconductors COMPARATOR The values of resistor components R process-dependent (see Parasitic resistance and capacitance from the pad are not included in this figure. Fig 27. ADC interface to pins AD0[n] Table 20. ADC interface components Component 13. DAC electrical characteristics Remark: The DAC is available on parts LPC1769/68/67/66/65/63. See Table 21 ...

  • Page 66

    ... NXP Semiconductors 14. Application information 14.1 Suggested USB interface solutions Remark: The USB controller is available as a device/Host/OTG controller on parts LPC1769/68/66/65 and as device-only controller on part LPC1764. LPC17xx Fig 28. USB interface on a self-powered device LPC17xx Fig 29. USB interface on a bus-powered device LPC1769_68_67_66_65_64_63 Product data sheet ...

  • Page 67

    ... NXP Semiconductors RSTOUT LPC17xx USB_SCL USB_SDA EINTn USB_D+ USB_D− USB_UP_LED Fig 30. USB OTG port configuration USB_UP_LED USB_D+ USB_D− LPC17xx USB_PWRD USB_OVRCR USB_PPWR Fig 31. USB host port configuration LPC1769_68_67_66_65_64_63 Product data sheet LPC1769/68/67/66/65/64/ RESET_N ADR/PSW OE_N/INT_N V DD SPEED ISP1302 SUSPEND ...

  • Page 68

    ... NXP Semiconductors USB_UP_LED USB_CONNECT LPC17xx USB_D+ USB_D− V BUS Fig 32. USB device port configuration 14.2 Crystal oscillator XTAL input and component selection The input voltage to the on-chip oscillators is limited to 1 the oscillator is driven by a clock in slave mode recommended that the input be coupled through a capacitor with C = 100 pF ...

  • Page 69

    ... NXP Semiconductors Fig 34. Oscillator modes and models: oscillation mode of operation and external crystal model used for C Table 22. Recommended values for C components parameters): low frequency mode Fundamental oscillation frequency F OSC 1 MHz - 5 MHz 5 MHz - 10 MHz 10 MHz - 15 MHz 15 MHz - 20 MHz Table 23. Recommended values for C ...

  • Page 70

    ... NXP Semiconductors order to keep the noise coupled in via the PCB as small as possible. Also parasitics should stay as small as possible. Values of C accordingly to the increase in parasitics of the PCB layout. 14.4 Standard I/O pin configuration Figure 35 shows the possible pin modes for standard I/O pins with analog input function: Digital output driver: Open-drain mode enabled/disabled • ...

  • Page 71

    ... NXP Semiconductors 14.5 Reset pin configuration reset Fig 36. Reset pin configuration LPC1769_68_67_66_65_64_63 Product data sheet LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller GLITCH FILTER All information provided in this document is subject to legal disclaimers. Rev. 6.01 — 11 March 2011 ESD PIN ESD V SS 002aaf274 © NXP B.V. 2011. All rights reserved. ...

  • Page 72

    ... NXP Semiconductors 15. Package outline LQFP100: plastic low profile quad flat package; 100 leads; body 1 pin 1 index 100 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 1.45 0.27 mm 1.6 0.25 0.05 1.35 0.17 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...

  • Page 73

    ... NXP Semiconductors TFBGA100: plastic thin fine-pitch ball grid array package; 100 balls; body 0.7 mm ball A1 index area ball index area DIMENSIONS (mm are the original dimensions) A UNIT max 0.4 0.8 0.5 9.1 mm 1.2 0.3 0.65 0.4 8.9 OUTLINE VERSION IEC SOT926 Fig 38. Package outline SOT926-1 (TFBGA100) ...

  • Page 74

    ... NXP Semiconductors 16. Abbreviations Table 24. Abbreviations Acronym ADC AHB AMBA APB BOD CAN DAC DMA EOP GPIO IRC IrDA JTAG MAC MIIM OHCI OTG PHY PLL PWM RIT RMII SE0 SPI SSI SSP TCM TTL UART USB LPC1769_68_67_66_65_64_63 Product data sheet LPC1769/68/67/66/65/64/63 ...

  • Page 75

    ... NXP Semiconductors 17. Revision history Table 25. Revision history Document ID Release date LPC1769_68_67_66_65_64_63 <tbd> v.6.01 Modifications: LPC1769_68_67_66_65_64_63 v.6 20100825 Modifications: LPC1769_68_67_66_65_64_63 v.5 20100716 LPC1769_68_67_66_65_64 v.4 20100201 LPC1768_67_66_65_64 v.3 20091119 LPC1768_66_65_64 v.2 20090211 LPC1768_66_65_64 v.1 20090115 LPC1769_68_67_66_65_64_63 Product data sheet LPC1769/68/67/66/65/64/63 Data sheet status ...

  • Page 76

    ... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...

  • Page 77

    ... Product data sheet LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. ...

  • Page 78

    ... NXP Semiconductors 20. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 4 4.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 4 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 6 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 8 7 Functional description . . . . . . . . . . . . . . . . . . 18 7.1 Architectural overview . . . . . . . . . . . . . . . . . . 18 7.2 ARM Cortex-M3 processor . . . . . . . . . . . . . . . 18 7.3 On-chip flash program memory . . . . . . . . . . . 18 7 ...

  • Page 79

    ... NXP Semiconductors 10 Static characteristics 10.1 Power consumption . . . . . . . . . . . . . . . . . . . . 47 10.2 Peripheral power consumption . . . . . . . . . . . . 49 10.3 Electrical pin characteristics . . . . . . . . . . . . . . 50 11 Dynamic characteristics . . . . . . . . . . . . . . . . . 52 11.1 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . 52 11.2 External clock . . . . . . . . . . . . . . . . . . . . . . . . . 52 11.3 Internal oscillators 11.4 I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 2 11.5 I C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 2 11.6 I S-bus interface . . . . . . . . . . . . . . . . . . . . . . 55 11.7 SSP interface . . . . . . . . . . . . . . . . . . . . . . . . . 57 11.8 USB interface ...