LPC2114FBD64/01,15 NXP Semiconductors, LPC2114FBD64/01,15 Datasheet
LPC2114FBD64/01,15
Specifications of LPC2114FBD64/01,15
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LPC2114FBD64/01-S
LPC2114FBD64/01-S
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LPC2114FBD64/01,15 Summary of contents
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LPC2114/2124 Single-chip 16/32-bit microcontrollers; 128/256 kB ISP/IAP flash with 10-bit ADC Rev. 06 — 10 December 2007 1. General description The LPC2114/2124 are based on a 16/32-bit ARM7TDMI-S CPU with real-time emulation and embedded trace support, together with 128/256 kB ...
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... NXP Semiconductors I 128/256 kB on-chip flash program memory. 128-bit wide interface/accelerator enables high speed 60 MHz operation. I In-System Programming (ISP) and In-Application Programming (IAP) via on-chip bootloader software. Flash programming takes 1 ms per 512 B line. Single sector or full chip erase takes 400 ms. ...
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... NXP Semiconductors 3.1 Ordering options Table 2. Type number LPC2114FBD64 LPC2114FBD64/00 LPC2114FBD64/01 LPC2124FBD64 LPC2124FBD64/00 LPC2124FBD64/01 LPC2114_2124_6 Product data sheet Ordering options Flash RAM memory 128 128 128 256 256 256 Rev. 06 — 10 December 2007 LPC2114/2124 Single-chip 16/32-bit microcontrollers Fast GPIO/SSP/ Temperature range ...
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... NXP Semiconductors 4. Block diagram LPC2114 LPC2124 HIGH-SPEED P0[30:27], (3) GPIO P0[25:0] 46 PINS TOTAL P1[31:16] ARM7 LOCAL BUS INTERNAL SRAM CONTROLLER 16 kB SRAM EXTERNAL (1) EINT[3:0] INTERRUPTS (1) 4 CAP0 CAPTURE/ (1) 4 CAP1 COMPARE (1) 4 MAT0 TIMER 0/TIMER 1 (1) 4 MAT1 (1) AIN[3:0] A/D CONVERTER P0[30:27], GENERAL ...
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... NXP Semiconductors 5. Pinning information 5.1 Pinning P0[21]/PWM5/CAP1[3] 1 P0[22]/CAP0[0]/MAT0[ P0[23] P1[19]/TRACEPKT3 4 P0[24 DDA(3V3) P1[18]/TRACEPKT2 8 P0[25 n.c. P0[27]/AIN0/CAP0[1]/MAT0[1] 11 P1[17]/TRACEPKT1 12 P0[28]/AIN1/CAP0[2]/MAT0[ P0[29]/AIN2/CAP0[3]/MAT0[3] P0[30]/AIN3/EINT3/CAP0[0] 15 P1[16]/TRACEPKT0 16 (1) Pin configuration is identical for devices with and without the /00 and /01 suffixes. ...
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... NXP Semiconductors 5.2 Pin description Table 3. Pin description Symbol Pin P0[0] to P0[31] P0[0]/TXD0/ 19 PWM1 P0[1]/RXD0/ 21 PWM3/EINT0 P0[2]/SCL/ 22 CAP0[0] P0[3]/SDA/ 26 MAT0[0]/EINT1 P0[4]/SCK0/ 27 CAP0[1] P0[5]/MISO0/ 29 MAT0[1] P0[6]/MOSI0/ 30 CAP0[2] P0[7]/SSEL0/ 31 PWM2/EINT2 P0[8]/TXD1/ 33 PWM4 P0[9]/RXD1/ ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Pin P0[15]/RI1/EINT2 45 P0[16]/EINT0/ 46 MAT0[2]/CAP0[2] P0[17]/CAP1[2]/ 47 SCK1/MAT1[2] P0[18]/CAP1[3]/ 53 MISO1/MAT1[3] P0[19]/MAT1[2]/ 54 MOSI1/CAP1[2] P0[20]/MAT1[3]/ 55 SSEL1/EINT3 P0[21]/PWM5/ 1 CAP1[3] P0[22]/CAP0[0]/ 2 MAT0[0] P0[23] 3 P0[24] 5 P0[25] 9 P0[27]/AIN0/ 11 CAP0[1]/MAT0[1] P0[28]/AIN1/ ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Pin P1[16]/ 16 TRACEPKT0 P1[17]/ 12 TRACEPKT1 P1[18]/ 8 TRACEPKT2 P1[19]/ 4 TRACEPKT3 P1[20]/ 48 TRACESYNC P1[21]/ 44 PIPESTAT0 P1[22]/ 40 PIPESTAT1 P1[23]/ 36 PIPESTAT2 P1[24]/ 32 TRACECLK P1[25]/EXTIN0 28 P1[26]/RTCK 24 P1[27]/TDO 64 P1[28]/TDI 60 P1[29]/TCK 56 P1[30]/TMS 52 P1[31]/TRST 20 n.c. ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Pin V 63 DDA(1V8) V 23, 43, 51 DD(3V3 DDA(3V3) [1] SSP interface available on LPC2114/01 and LPC2124/01 only. LPC2114_2124_6 Product data sheet Type Description I analog 1.8 V core power supply; this is the power supply voltage for internal circuitry. This should be nominally the same voltage as V isolated to minimize noise and error ...
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... NXP Semiconductors 6. Functional description Details of the LPC2114/2124 systems and peripheral functions are described in the following sections. 6.1 Architectural overview The ARM7TDMI general purpose 32-bit microprocessor, which offers high performance and very low power consumption. The ARM architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and related decode mechanism are much simpler than those of microprogrammed Complex Instruction Set Computers ...
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... NXP Semiconductors However, the ISP flash erase command can be executed at any time (no matter whether the CRP off). Removal of CRP is achieved by erasure of full on-chip user flash. With the CRP off, full access to the chip via the JTAG and/or ISP is restored. 6.3 On-chip static RAM On-chip static RAM may be used for code and/or data storage ...
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... NXP Semiconductors Fig 3. LPC2114/2124 memory map 6.5 Interrupt controller The Vectored Interrupt Controller (VIC) accepts all of the interrupt request inputs and categorizes them as Fast Interrupt Request (FIQ), vectored Interrupt Request (IRQ), and non-vectored IRQ as defined by programmable settings. The programmable assignment scheme means that priorities of interrupts from the various peripherals can be dynamically assigned and adjusted ...
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... NXP Semiconductors Vectored IRQs have the middle priority. Sixteen of the interrupt requests can be assigned to this category. Any of the interrupt requests can be assigned to any of the 16 vectored IRQ slots, among which slot 0 has the highest priority and slot 15 has the lowest. Non-vectored IRQs have the lowest priority. ...
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... NXP Semiconductors Table 4. Block System Control ADC [1] SSP interface available on LPC2114/01 and LPC2124/01 only. 6.6 Pin connect block The pin connect block allows selected pins of the microcontroller to have more than one function. Configuration registers control the multiplexers to allow connection between the pin and the on chip peripherals ...
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... NXP Semiconductors 6.8.1 Features • Measurement range • Capable of performing more than 400000 10-bit samples per second. • Burst conversion mode for single or multiple inputs. • Optional conversion on transition on input pin or Timer Match signal. • Every analog input has a dedicated result register to reduce interrupt overhead. ...
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... NXP Semiconductors the capability to both receive and send information (such as memory). Transmitters and/or receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed. The I controlled by more than one bus master connected to it. 2 The I ...
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... NXP Semiconductors 6.12 SSP controller (LPC2114/2124/01 only) Remark: This peripheral is available in LPC2114/2124/01 only. The SSP is a controller capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus. Only a single master and a single slave can communicate on the bus during a given data transfer. Data transfers are in principle full duplex, with frames of four to 16 bits of data fl ...
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... NXP Semiconductors 6.13.2 Features available in LPC2114/2124/01 only • Timer can count cycles of either the peripheral clock (PCLK externally supplied clock. • When counting cycles of an externally supplied clock only one of timer’s capture inputs can be selected as the timer’s clock. The rate of such a clock is limited to PCLK / 4 ...
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... NXP Semiconductors 6.16 Pulse width modulator The PWM is based on the standard Timer block and inherits all of its features, although only the PWM function is pinned out on the LPC2114/2124. The Timer is designed to count cycles of the peripheral clock (PCLK) and optionally generate interrupts or perform other actions when specifi ...
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... NXP Semiconductors • Match register updates are synchronized with pulse outputs to prevent generation of erroneous pulses. Software must ‘release’ new match values before they can become effective. • May be used as a standard timer if the PWM mode is not enabled. • A 32-bit Timer/Counter with a programmable 32-bit Prescaler. ...
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... NXP Semiconductors The Wake-up Timer monitors the crystal oscillator as the means of checking whether it is safe to begin code execution. When power is applied to the chip, or some event caused the chip to exit Power-down mode, some time is required for the oscillator to produce a signal of sufficient amplitude to drive the clock logic. The amount of time depends on ...
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... NXP Semiconductors 6.17.7 Power control The LPC2114/2124 support two reduced power modes: Idle mode and Power-down mode. In Idle mode, execution of instructions is suspended until either a Reset or interrupt occurs. Peripheral functions continue operation during Idle mode and may generate interrupts to cause the processor to resume execution. Idle mode eliminates power used by the processor itself, memory systems and related controllers, and internal buses ...
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... NXP Semiconductors communication channel allows the JTAG port to be used for sending and receiving data without affecting the normal program flow. The debug communication channel data and control registers are mapped in to addresses in the EmbeddedICE logic. The JTAG clock (TCK) must be slower than interface to operate ...
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... NXP Semiconductors 7. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage (1.8 V) DD(1V8) V supply voltage (3.3 V) DD(3V3) V analog supply voltage (3.3 V) DDA(3V3) V analog input voltage IA V input voltage I I supply current DD I ground current ...
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... NXP Semiconductors 8. Static characteristics Table 6. Static characteristics +85 C for industrial applications, unless otherwise specified. amb Symbol Parameter V supply voltage (1.8 V) DD(1V8) V supply voltage (3.3 V) DD(3V3) V analog supply voltage DDA(3V3) (3.3 V) Standard port pins, RESET, RTCK I LOW-state input current IL I HIGH-state input current ...
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... NXP Semiconductors Table 6. Static characteristics +85 C for industrial applications, unless otherwise specified. amb Symbol Parameter Power consumption LPC2114/01 and LPC2124/01 I active mode supply current DD(act) I Idle mode supply current DD(idle) I Power-down mode supply DD(pd) current 2 I C-bus pins V HIGH-state input voltage ...
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... NXP Semiconductors Table 7. ADC static characteristics 3.6 V unless otherwise specified; T DDA 4.5 MHz. Symbol Parameter V analog input voltage IA C analog input ia capacitance E differential linearity D error E integral non-linearity L(adj) E offset error O E gain error G E absolute error T [1] Conditions 3.3 V. ...
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... NXP Semiconductors 1023 1022 1021 1020 1019 1018 7 code out offset error E O (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (E (4) Integral non-linearity (E L(adj) (5) Center of a step of the actual transfer curve. Fig 4. ADC characteristics LPC2114_2124_6 Product data sheet ...
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... NXP Semiconductors 8.1 Power consumption measurements for LPC2114/01 and LPC2124/01 The power consumption measurements represent typical values for the given conditions. The peripherals were enabled through the PCONP register, but for these measurements, the peripherals were not configured to run. Peripherals were disabled through the PCONP register ...
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... NXP Semiconductors 50 I DD(act) (mA 1.65 Test conditions: Active mode entered executing code from on-chip flash; PCLK = core voltage 1.8 V; all peripherals enabled. amb Fig 7. Typical LPC2114/01 and LPC2124/ DD(idle) (mA Test conditions: Idle mode entered executing code from on-chip flash; PCLK = core voltage 1.8 V. ...
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... NXP Semiconductors 10 I DD(idle) (mA 1.65 Test conditions: Idle mode entered executing code from on-chip flash; PCLK = core voltage 1.8 V; all peripherals enabled. amb Fig 9. Typical LPC2114/01 and LPC2124/ DD(idle) (mA 1.65 Test conditions: Idle mode entered executing code from on-chip flash; PCLK = Temp = 25 C ...
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... NXP Semiconductors 45 I DD(act) (mA -40 -15 Test conditions: Active mode entered executing code from on-chip flash; PCLK = core voltage 1.8 V; all peripherals disabled. Fig 11. Typical LPC2114/01 and LPC2124/01 I 6.0 I DD(idle) (mA) 5.0 4.0 3.0 2.0 1.0 0.0 -40 -15 Test conditions: Idle mode entered executing code from on-chip flash; PCLK = core voltage 1.8 V ...
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... NXP Semiconductors 200 I DD(pd 160 120 -40 -15 Test conditions: Power-down mode entered executing code from on-chip flash. Fig 13. Typical LPC2114/01 and LPC2124/01 core power-down current I Table 8. Core voltage 1 Peripheral Timer0 Timer1 UART0 UART1 PWM0 2 I C-bus SPI0/1 RTC ADC LPC2114_2124_6 Product data sheet ...
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... NXP Semiconductors 9. Dynamic characteristics Table 9. Dynamic characteristics +85 C for industrial applications; V amb Symbol Parameter External clock f oscillator frequency osc T clock cycle time cy(clk) t clock HIGH time CHCX t clock LOW time CLCX t clock rise time CLCH t clock fall time CHCL Port pins (except P0[2] and P0[3]) ...
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... NXP Semiconductors 9.1 Timing V Fig 14. External clock timing LPC2114_2124_6 Product data sheet 0 0.2V 0 0. CHCL Rev. 06 — 10 December 2007 LPC2114/2124 Single-chip 16/32-bit microcontrollers t CHCX t t CLCX CLCH T cy(clk) 002aaa907 © NXP B.V. 2007. All rights reserved ...
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... NXP Semiconductors 10. Package outline LQFP64: plastic low profile quad flat package; 64 leads; body 1 pin 1 index DIMENSIONS (mm are the original dimensions) A UNIT max. 0.20 1.45 mm 1.6 0.25 0.05 1.35 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION ...
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... NXP Semiconductors 11. Abbreviations Table 10. Acronym ADC AMBA APB CPU DAC DCC FIFO GPIO I/O JTAG PLL PWM RAM SPI SRAM SSI SSP TTL UART LPC2114_2124_6 Product data sheet Abbreviations Description Analog-to-Digital Converter Advanced Microcontroller Bus Architecture Advanced Peripheral Bus Central Processing Unit ...
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... LPC2114_2124_6 20071210 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Type number LPC2114FBD64/01 has been added. • ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 15. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.1 Key features brought by LPC2114/2124/01 devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.2 Key features common for all devices . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 3.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 Functional description . . . . . . . . . . . . . . . . . . 10 6.1 Architectural overview ...