ST72F260G1M6 STMicroelectronics, ST72F260G1M6 Datasheet
ST72F260G1M6
Specifications of ST72F260G1M6
Available stocks
Related parts for ST72F260G1M6
ST72F260G1M6 Summary of contents
Page 1
ADC, TWO 16-BIT TIMERS, I Memories ■ – Kbytes Program memory: ROM or Single voltage extended Flash (XFlash) with read-out protection write protection and In- Circuit Programming and In-Application Pro- gramming (ICP and IAP). 10K write/erase ...
Page 2
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 3
I/O PORT INTERRUPT SENSITIVITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 4
ST72260Gx, ST72262Gx, ST72264Gx To obtain the most recent version of this datasheet, please check at www.st.com>products>technical literature>datasheet Please note that the list of known limitations can be found at the end of this document on 4/172 page 168. ...
Page 5
INTRODUCTION The ST72260Gx, ST72262Gx and ST72264Gx devices are members of the ST7 microcontroller family. They can be grouped as follows : – ST72264Gx devices are designed for mid-range 2 applications with ADC and SCI interface ca- pabilities. ...
Page 6
ST72260Gx, ST72262Gx, ST72264Gx 2 PIN DESCRIPTION Figure 2. 28-Pin SO Package Pinout OCMP2_A/PB3 ICAP2_A/PB2 OCMP1_A/PB1 ICAP1_A/PB0 AIN5/EXTCLK_A/PC5 2 AIN4 /OCMP2_B/PC4 2 AIN3 /ICAP2_B/PC3 1 Configurable by option byte 2 Alternate function not available on ST72260 3 Alternate function not available ...
Page 7
PIN DESCRIPTION (Cont’d) Figure 4. TFBGA Package Pinout (view through package ST72260Gx, ST72262Gx, ST72264Gx 7/172 ...
Page 8
ST72260Gx, ST72262Gx, ST72264Gx PIN DESCRIPTION (Cont’d) For external pin connection guidelines, refer to 126. Legend / Abbreviations for Type input output supply Input level Dedicated analog input In/Output level CMOS ...
Page 9
Pin n° Pin Name PC4/OCMP2_B/AIN4 PC3/ ICAP2_B/AIN3 PC2/MCO/AIN2 PC1/OCMP1_B/AIN1 PC0/ICAP1_B/AIN0 PA7/TDO PA6/SDAI PA5 /RDI 23 21 ...
Page 10
ST72260Gx, ST72262Gx, ST72264Gx 3 REGISTER & MEMORY MAP As shown in Figure 5, the MCU is capable of ad- dressing 64K bytes of memories and I/O registers. The available memory locations consist of 128 bytes of register location, 256 bytes ...
Page 11
Table 2. Hardware Register Map Register Address Block 0000h PCDR 0001h Port C PCDDR 0002h PCOR 0003h 0004h PBDR 0005h Port B PBDDR 0006h PBOR 0007h 0008h PADR 0009h Port A PADDR 000Ah PAOR 000Bh to 001Bh 001Ch ISPR0 001Dh ...
Page 12
ST72260Gx, ST72262Gx, ST72264Gx Register Address Block 0031h TACR2 0032h TACR1 0033h TASCSR 0034h TAIC1HR 0035h TAIC1LR 0036h TAOC1HR 0037h TAOC1LR 0038h TIMER A TACHR 0039h TACLR 003Ah TAACHR 003Bh TAACLR 003Ch TAIC2HR 003Dh TAIC2LR 003Eh TAOC2HR 003Fh TAOC2LR 0040h MISCR2 ...
Page 13
Legend: x=Undefined, R/W=Read/Write Notes: 1. The contents of the I/O port DR registers are readable only in output configuration. In input configura- tion, the values of the I/O pins are returned instead of the DR register contents. 2. The bits ...
Page 14
ST72260Gx, ST72262Gx, ST72264Gx 4 FLASH PROGRAM MEMORY 4.1 Introduction The ST7 single voltage extended Flash (XFlash non-volatile memory that can be electrically erased and programmed either on a byte-by-byte basis bytes in parallel. The ...
Page 15
FLASH PROGRAM MEMORY (Cont’d) 4.4 ICC interface ICP needs a minimum of 4 and pins to be connected to the programming tool. These pins are: – RESET: device reset – device power supply ground SS ...
Page 16
ST72260Gx, ST72262Gx, ST72264Gx FLASH PROGRAM MEMORY (Cont’d) 4.5 Memory Protection There are two different types of memory protec- tion: Read Out Protection and Write/Erase Protec- tion which can be applied individually. 4.5.1 Read out Protection Read-out protection, when selected, provides ...
Page 17
CENTRAL PROCESSING UNIT 5.1 INTRODUCTION This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 5.2 MAIN FEATURES Enable executing 63 basic instructions ■ Fast 8-bit by 8-bit multiply ■ 17 main ...
Page 18
ST72260Gx, ST72262Gx, ST72264Gx CENTRAL PROCESSING UNIT (Cont’d) Condition Code Register (CC) Read/Write Reset Value: 111x1xxx The 8-bit Condition Code register contains the in- terrupt masks and four flags representative of the result of the ...
Page 19
CENTRAL PROCESSING UNIT (Cont’d) Stack Pointer (SP) Read/Write Reset Value: 01 7Fh SP7 SP6 SP5 SP4 SP3 The Stack Pointer is a 16-bit register which is al- ways pointing to the next free ...
Page 20
ST72260Gx, ST72262Gx, ST72264Gx 6 SUPPLY, RESET AND CLOCK MANAGEMENT The device includes a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and re- ducing the number of external components. ...
Page 21
MULTI-OSCILLATOR (MO) The main clock of the ST7 can be generated by four different source types coming from the multi- oscillator block: an external source ■ 5 crystal or ceramic resonator oscillators ■ an internal high frequency RC oscillator ...
Page 22
ST72260Gx, ST72262Gx, ST72264Gx 6.3 RESET SEQUENCE MANAGER (RSM) 6.3.1 Introduction The reset sequence manager includes three RE- SET sources as shown in Figure External RESET source pulse ■ Internal LVD RESET (Low Voltage Detection) ■ Internal WATCHDOG RESET ■ These ...
Page 23
RESET SEQUENCE MANAGER (Cont’d) The RESET pin is an asynchronous signal which plays a major role in EMS performance noisy environment recommended to follow the guidelines mentioned in the electrical characteris- tics section. 6.3.3 External Power-On ...
Page 24
ST72260Gx, ST72262Gx, ST72264Gx 6.4 SYSTEM INTEGRITY MANAGEMENT (SI) The System Integrity Management block contains group the Low voltage Detector (LVD) and Auxilia- ry Voltage Detector (AVD) functions managed by the SICSR register. Note: A reset can also be ...
Page 25
SYSTEM INTEGRITY MANAGEMENT (Cont’d) 6.4.2 Auxiliary Voltage Detector (AVD) The Voltage Detector function (AVD) is based on an analog comparison between a V erence value and the V main supply. The V DD reference value for falling voltage is lower ...
Page 26
ST72260Gx, ST72262Gx, ST72264Gx SYSTEM INTEGRITY MANAGEMENT (Cont’d) 6.4.3 Low Power Modes Mode Description No effect on SI. AVD interrupts cause the WAIT device to exit from Wait mode. HALT The SICSR register is frozen. 6.4.3.1 Interrupts The AVD interrupt event ...
Page 27
SYSTEM INTEGRITY MANAGEMENT (Cont’d) 6.4.4 Register Description SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR) Read/Write Reset Value: 000x 000x (00h) 7 AVD AVD LVD Bit 7 = Reserved, always read as 0. Bit 6 = AVDIE ...
Page 28
ST72260Gx, ST72262Gx, ST72264Gx 7 INTERRUPTS 7.1 INTRODUCTION The ST7 enhanced interrupt management pro- vides the following features: Hardware interrupts ■ Software interrupt (TRAP) ■ Nested or concurrent interrupt management ■ with flexible interrupt management: – software programmable ...
Page 29
INTERRUPTS (Cont’d) Servicing Pending Interrupts As several interrupts can be pending at the same time, the interrupt to be taken into account is deter- mined by the following two-step process: – the highest software priority interrupt is serviced, – if ...
Page 30
ST72260Gx, ST72262Gx, ST72264Gx INTERRUPTS (Cont’d) 7.3 INTERRUPTS AND LOW POWER MODES All interrupts allow the processor to exit the WAIT low power mode. On the contrary, only external and other specified interrupts allow the processor to exit the HALT modes ...
Page 31
INTERRUPTS (Cont’d) 7.5 INTERRUPT REGISTER DESCRIPTION CPU CC REGISTER INTERRUPT BITS Read/Write Reset Value: 111x 1010 (xAh Bit I1, I0 Software Interrupt Priority These two bits indicate the current interrupt soft- ...
Page 32
ST72260Gx, ST72262Gx, ST72264Gx INTERRUPTS (Cont’d) Table 5. Interrupt Mapping Source N° Block RESET Reset TRAP Software Interrupt 0 ei0 External Interrupt Port A7..0 (C5..0 1 ei1 External Interrupt Port B7..0 (C5..0 2 Not used 3 SPI SPI Peripheral Interrupts 4 ...
Page 33
POWER SAVING MODES 8.1 INTRODUCTION To give a large measure of flexibility to the applica- tion in terms of power consumption, three main power saving modes are implemented in the ST7 (see Figure 20). After a RESET the normal ...
Page 34
ST72260Gx, ST72262Gx, ST72264Gx POWER SAVING MODES (Cont’d) 8.3 WAIT MODE WAIT mode places the MCU in a low power con- sumption mode by stopping the CPU. This power saving mode is selected by calling the “WFI” ST7 software instruction. All ...
Page 35
ACTIVE-HALT AND HALT MODES ACTIVE-HALT and HALT modes are the two low- est power consumption modes of the MCU. They are both entered by executing the ‘HALT’ instruc- tion. The decision to enter either in ACTIVE-HALT or HALT mode ...
Page 36
ST72260Gx, ST72262Gx, ST72264Gx POWER SAVING MODES (Cont’d) 8.5 HALT MODE The HALT mode is the lowest power consumption mode of the MCU entered by executing the ST7 HALT instruction (see Figure The MCU can exit HALT mode on ...
Page 37
POWER SAVING MODES (Cont’d) 8.5.0.1 Halt Mode Recommendations – Make sure that an external event is available to wake up the microcontroller from Halt mode. – When using an external interrupt to wake up the microcontroller, reinitialize the corresponding I/O ...
Page 38
ST72260Gx, ST72262Gx, ST72264Gx 9 I/O PORTS 9.1 INTRODUCTION The I/O ports allow data transfer. An I/O port can contain pins. Each pin can be programmed independently either as a digital input or digital output. In addition, specific ...
Page 39
I/O PORTS (Cont’d) Figure 27. I/O Port General Block Diagram ALTERNATE REGISTER OUTPUT ACCESS From on-chip periphera ALTERNATE ENABLE BIT DR DDR OR If implemented OR SEL DDR SEL DR SEL 1 0 EXTERNAL Combinational INTERRUPT REQUEST ( ...
Page 40
ST72260Gx, ST72262Gx, ST72264Gx I/O PORTS (Cont’d) Table 8. I/O Configurations V PAD V PAD PAD Notes: 1. When the I/O port is in input configuration and the associated alternate function is enabled as an output, reading the DR register will ...
Page 41
I/O PORTS (Cont’d) Analog alternate function Configure the I/O as floating input to use an ADC input. The analog multiplexer (controlled by the ADC registers) switches the analog voltage present on the selected pin to the common analog rail, connected ...
Page 42
ST72260Gx, ST72262Gx, ST72264Gx I/O PORTS (Cont’d) 9.7 DEVICE-SPECIFIC I/O PORT CONFIGURATION The I/O port register configurations are summa- rised as follows. Interrupt Ports PA7, PA5, PA3:0, PB7:0, PC5:0 (with pull-up) MODE floating input pull-up interrupt input open drain output push-pull ...
Page 43
I/O PORTS (Cont’d) 9.8 I/O PORT REGISTER DESCRIPTION DATA REGISTER (DR) Port x Data Register PxDR with Read/Write Reset Value: 0000 0000 (00h Bits 7:0 = D[7:0] Data ...
Page 44
ST72260Gx, ST72262Gx, ST72264Gx I/O PORTS (Cont’d) Table 10. I/O Port Register Map and Reset Values Address Register 7 Label (Hex.) Reset Value of all I/O port registers 0000h PCDR 0001h PCDDR MSB 0002h PCOR 0004h PBDR 0005h PBDDR MSB 0006h ...
Page 45
MISCELLANEOUS REGISTERS The miscellaneous registers allow control over several different features such as the external in- terrupts or the I/O alternate functions. 10.1 I/O PORT INTERRUPT SENSITIVITY The external interrupt sensitivity is controlled by the ISxx bits of the ...
Page 46
ST72260Gx, ST72262Gx, ST72264Gx MISCELLANEOUS REGISTERS (Cont’d) 10.3 MISCELLANEOUS REGISTER DESCRIPTION MISCELLANEOUS REGISTER 1 (MISCR1) Read/Write Reset Value: 0000 0000 (00h) 7 IS11 IS10 MCO IS01 IS00 Bits 7:6 = IS1[1:0] ei1 sensitivity The interrupt sensitivity, defined using the IS1[1:0] bits, ...
Page 47
MISCELLANEOUS REGISTERS (Cont’d) MISCELLANEOUS REGISTER 2 (MISCR2) Read/Write Reset Value: 0000 0000 (00h MOD SOD SSM Caution: This register has been provided for com- patibility with the ST72254 family only. The same bits are available ...
Page 48
ST72260Gx, ST72262Gx, ST72264Gx 11 ON-CHIP PERIPHERALS 11.1 WATCHDOG TIMER (WDG) 11.1.1 Introduction The Watchdog timer is used to detect the occur- rence of a software fault, usually generated by ex- ternal interference or by unforeseen logical condi- tions, which causes ...
Page 49
WATCHDOG TIMER (Cont’d) 11.1.4 How to Program the Watchdog Timeout Figure 32 shows the linear relationship between the 6-bit value to be loaded in the Watchdog Coun- ter (CNT) and the resulting timeout duration in mil- liseconds. This can be ...
Page 50
ST72260Gx, ST72262Gx, ST72264Gx WATCHDOG TIMER (Cont’d) Figure 33. Exact Timeout Duration (t WHERE (LSB + 128 min0 OSC2 t = 16384 x t max0 OSC2 t = 125ns MHz OSC2 OSC2 ...
Page 51
WATCHDOG TIMER (Cont’d) 11.1.5 Low Power Modes Mode Description SLOW No effect on Watchdog. WAIT No effect on Watchdog. OIE bit in WDGHALT bit MCCSR in Option register Byte 0 HALT 0 1 11.1.6 Hardware Watchdog Option If Hardware Watchdog ...
Page 52
ST72260Gx, ST72262Gx, ST72264Gx Table 12. Watchdog Timer Register Map and Reset Values Address Register 7 Label (Hex.) WDGCR WDGA 0024h Reset Value 0 52/172 ...
Page 53
MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (MCC/RTC) The Main Clock Controller consists of a real time clock timer with interrupt capability 11.2.1 Real Time Clock Timer (RTC) The counter of the real time clock timer allows an interrupt ...
Page 54
ST72260Gx, ST72262Gx, ST72264Gx MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont’d) 11.2.2 Low Power Modes Mode Description No effect on MCC/RTC peripheral. WAIT MCC/RTC interrupt cause the device to exit from WAIT mode. No effect on MCC/RTC counter (OIE bit ...
Page 55
TIMER 11.3.1 Introduction The timer consists of a 16-bit free-running counter driven by a programmable prescaler. It may be used for a variety of purposes, including pulse length measurement two input sig- nals (input capture) ...
Page 56
ST72260Gx, ST72262Gx, ST72264Gx 16-BIT TIMER (Cont’d) Figure 35. Timer Block Diagram f CPU 8 high EXEDG 1/2 COUNTER 1/4 REGISTER 1/8 ALTERNATE EXTCLK pin COUNTER REGISTER CC[1:0] OVERFLOW DETECT CIRCUIT ICF1 OCF1 TOF ICF2 (Control/Status Register) ICIE OCIE TOIE FOLV2 ...
Page 57
TIMER (Cont’d) 16-bit read sequence: (from either the Counter Register or the Alternate Counter Register). Beginning of the sequence Read MS Byte At t0 Other instructions Read At t0 +∆t LS Byte Sequence completed The user must read the ...
Page 58
ST72260Gx, ST72262Gx, ST72264Gx 16-BIT TIMER (Cont’d) Figure 36. Counter Timing Diagram, internal clock divided by 2 CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER TIMER OVERFLOW FLAG (TOF) Figure 37. Counter Timing Diagram, internal clock divided by 4 CPU CLOCK ...
Page 59
TIMER (Cont’d) 11.3.3.3 Input Capture In this section, the index, i, may because there are 2 input capture functions in the 16-bit timer. The two input capture 16-bit registers (IC1R and IC2R) are used to ...
Page 60
ST72260Gx, ST72262Gx, ST72264Gx 16-BIT TIMER (Cont’d) Figure 39. Input Capture Block Diagram ICAP1 pin EDGE DETECT CIRCUIT2 ICAP2 pin IC2R Register 16-BIT 16-BIT FREE RUNNING COUNTER Figure 40. Input Capture Timing Diagram TIMER CLOCK COUNTER REGISTER ICAPi PIN ICAPi FLAG ...
Page 61
TIMER (Cont’d) 11.3.3.4 Output Compare In this section, the index, i, may because there are 2 output compare functions in the 16-bit timer. This function can be used to control an output waveform or indicate ...
Page 62
ST72260Gx, ST72262Gx, ST72264Gx 16-BIT TIMER (Cont’d) Notes: 1. After a processor write cycle to the OCiHR reg- ister, the output compare function is inhibited until the OCiLR register is also written the OCiE bit is not set, the ...
Page 63
TIMER (Cont’d) Figure 42. Output Compare Timing Diagram, f INTERNAL CPU CLOCK COUNTER REGISTER OUTPUT COMPARE REGISTER i (OCRi) OUTPUT COMPARE FLAG i (OCFi) OCMPi PIN (OLVLi=1) Figure 43. Output Compare Timing Diagram, f INTERNAL CPU CLOCK COUNTER REGISTER ...
Page 64
ST72260Gx, ST72262Gx, ST72264Gx 16-BIT TIMER (Cont’d) 11.3.3.5 One Pulse Mode One Pulse mode enables the generation of a pulse when an external event occurs. This mode is selected via the OPM bit in the CR2 register. The one pulse mode ...
Page 65
TIMER (Cont’d) Figure 44. One Pulse Mode Timing Example IC1R 01F8 COUNTER ICAP1 OCMP1 Note: IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1 Figure 45. Pulse Width Modulation Mode Timing Example FFFC FFFD FFFE COUNTER 34E2 OCMP1 compare2 Note: OC1R=2ED0h, OC2R=34E2, OLVL1=0, OLVL2= ...
Page 66
ST72260Gx, ST72262Gx, ST72264Gx 16-BIT TIMER (Cont’d) 11.3.3.6 Pulse Width Modulation Mode Pulse Width Modulation (PWM) mode enables the generation of a signal with a frequency and pulse length determined by the value of the OC1R and OC2R registers. Pulse Width ...
Page 67
TIMER (Cont’ PWM mode the ICAP1 pin can not be used to perform input capture because it is discon- nected to the timer. The ICAP2 pin can be used to perform input capture (ICF2 can be set ...
Page 68
ST72260Gx, ST72262Gx, ST72264Gx 16-BIT TIMER (Cont’d) 11.3.7 Register Description Each Timer is associated with three control and status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compares, the counter ...
Page 69
TIMER (Cont’d) CONTROL REGISTER 2 (CR2) Read/Write Reset Value: 0000 0000 (00h) 7 OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG Bit 7 = OC1E Output Compare 1 Pin Enable. This bit is used only to output the signal ...
Page 70
ST72260Gx, ST72262Gx, ST72264Gx 16-BIT TIMER (Cont’d) CONTROL/STATUS REGISTER (CSR) Read Only Reset Value: 0000 0000 (00h) The three least significant bits are not used. 7 ICF1 OCF1 TOF ICF2 OCF2 TIMD Bit 7 = ICF1 Input Capture Flag 1. 0: ...
Page 71
TIMER (Cont’d) INPUT CAPTURE 1 HIGH REGISTER (IC1HR) Read Only Reset Value: Undefined This is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 1 event). 7 MSB INPUT ...
Page 72
ST72260Gx, ST72262Gx, ST72264Gx 16-BIT TIMER (Cont’d) OUTPUT COMPARE 2 (OC2HR) Read/Write Reset Value: 1000 0000 (80h) This is an 8-bit register that contains the high part of the value to be compared to the CHR register. 7 MSB OUTPUT COMPARE ...
Page 73
TIMER (Cont’d) Table 15. 16-Bit Timer Register Map and Reset Values Address Register 7 Label (Hex.) Timer A: 32 CR1 ICIE Timer B: 42 Reset Value Timer A: 31 CR2 OC1E Timer B: 41 Reset Value Timer A: 33 ...
Page 74
ST72260Gx, ST72262Gx, ST72264Gx 16-BIT TIMER (Cont’d) Related Documentation AN 973: SCI software communications using 16- bit timer AN 974: Real Time Clock with ST7 Timer Output Compare AN 976: Driving a buzzer through the ST7 Timer PWM function 74/172 AN1041: ...
Page 75
SERIAL PERIPHERAL INTERFACE (SPI) 11.4.1 Introduction The Serial Peripheral Interface (SPI) allows full- duplex, synchronous, serial communication with external devices. An SPI system may consist of a master and one or more slaves or a system in which devices ...
Page 76
ST72260Gx, ST72262Gx, ST72264Gx SERIAL PERIPHERAL INTERFACE (Cont’d) Figure 46. Serial Peripheral Interface Block Diagram SPIDR Read Buffer MOSI MISO 8-Bit Shift Register SOD bit SCK SS 76/172 Data/Address Bus Read 7 SPIF WCOL Write 7 SPIE MASTER CONTROL SERIAL CLOCK ...
Page 77
SERIAL PERIPHERAL INTERFACE (Cont’d) 11.4.3.1 Functional Description A basic example of interconnections between a single master and a single slave is illustrated in Figure 47. The MOSI pins are connected together and the MISO pins are connected together. In this ...
Page 78
ST72260Gx, ST72262Gx, ST72264Gx SERIAL PERIPHERAL INTERFACE (Cont’d) 11.4.3.2 Slave Select Management As an alternative to using the SS pin to control the Slave Select signal, the application can choose to manage the Slave Select signal by software. This is configured ...
Page 79
SERIAL PERIPHERAL INTERFACE (Cont’d) 11.4.3.3 Master Mode Operation In master mode, the serial clock is output on the SCK pin. The clock frequency, polarity and phase are configured by software (refer to the description of the SPICSR register). Note: The ...
Page 80
ST72260Gx, ST72262Gx, ST72264Gx SERIAL PERIPHERAL INTERFACE (Cont’d) 11.4.4 Clock Phase and Clock Polarity Four possible timing relationships may be chosen by software, using the CPOL and CPHA bits (See Figure 50). Note: The idle state of SCK must correspond to ...
Page 81
SERIAL PERIPHERAL INTERFACE (Cont’d) 11.4.5 Error Flags 11.4.5.1 Master Mode Fault (MODF) Master mode fault occurs when the master device has its SS pin pulled low. When a Master mode fault occurs: – The MODF bit is set and an ...
Page 82
ST72260Gx, ST72262Gx, ST72264Gx SERIAL PERIPHERAL INTERFACE (Cont’d) 11.4.5.4 Single Master Configurations There are two types of SPI systems: – Single Master System – Multimaster System Single Master System A typical single master system may be configured, using a as the ...
Page 83
SERIAL PERIPHERAL INTERFACE (Cont’d) 11.4.6 Low Power Modes Mode Description No effect on SPI. WAIT SPI interrupt events cause the Device to exit from WAIT mode. SPI registers are frozen. In HALT mode, the SPI is inactive. SPI oper- ation ...
Page 84
ST72260Gx, ST72262Gx, ST72264Gx SERIAL PERIPHERAL INTERFACE (Cont’d) 11.4.8 Register Description CONTROL REGISTER (SPICR) Read/Write Reset Value: 0000 xxxx (0xh) 7 SPIE SPE SPR2 MSTR CPOL Bit 7 = SPIE Serial Peripheral Interrupt Enable. This bit is set and cleared by ...
Page 85
SERIAL PERIPHERAL INTERFACE (Cont’d) CONTROL/STATUS REGISTER (SPICSR) Read/Write (some bits Read Only) Reset Value: 0000 0000 (00h) 7 SPIF WCOL OVR MODF Bit 7 = SPIF Serial Peripheral Data Transfer Flag (Read only). This bit is set by hardware when ...
Page 86
ST72260Gx, ST72262Gx, ST72264Gx SERIAL PERIPHERAL INTERFACE (Cont’d) Table 17. SPI Register Map and Reset Values Address Register 7 Label (Hex.) SPIDR MSB 0021h Reset Value SPICR SPIE 0022h Reset Value SPICSR SPIF 0023h Reset Value 86/172 ...
Page 87
SERIAL COMMUNICATIONS INTERFACE (SCI) 11.5.1 Introduction The Serial Communications Interface (SCI) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format. The SCI of- fers a very wide range ...
Page 88
ST72260Gx, ST72262Gx, ST72264Gx SERIAL COMMUNICATIONS INTERFACE (Cont’d) Figure 53. SCI Block Diagram Write Transmit Data Register (TDR) TDO Transmit Shift Register RDI TRANSMIT CONTROL CR2 TIE TCIE RIE SCI INTERRUPT CONTROL TRANSMITTER CLOCK f CPU 88/172 Read Received Data Register ...
Page 89
SERIAL COMMUNICATIONS INTERFACE (Cont’d) 11.5.4 Functional Description The block diagram of the Serial Control Interface, is shown in Figure 53. It contains 6 dedicated reg- isters: – Two control registers (SCICR1 & SCICR2) – A status register (SCISR) – A ...
Page 90
ST72260Gx, ST72262Gx, ST72264Gx SERIAL COMMUNICATIONS INTERFACE (Cont’d) 11.5.4.2 Transmitter The transmitter can send data words of either bits depending on the M bit status. When the M bit is set, word length is 9 bits and the ...
Page 91
SERIAL COMMUNICATIONS INTERFACE (Cont’d) 11.5.4.3 Receiver The SCI can receive data words of either bits. When the M bit is set, word length is 9 bits and the MSB is stored in the R8 bit in the ...
Page 92
ST72260Gx, ST72262Gx, ST72264Gx SERIAL COMMUNICATIONS INTERFACE (Cont’d) Figure 55. SCI Baud Rate and Extended Prescaler Block Diagram EXTENDED PRESCALER TRANSMITTER RATE CONTROL EXTENDED TRANSMITTER PRESCALER REGISTER EXTENDED RECEIVER PRESCALER REGISTER EXTENDED PRESCALER RECEIVER RATE CONTROL f CPU /PR /16 SCP1 ...
Page 93
SERIAL COMMUNICATIONS INTERFACE (Cont’d) Framing Error A framing error is detected when: – The stop bit is not recognized on reception at the expected time, following either a de-synchroni- zation or excessive noise. – A break is received. When the ...
Page 94
ST72260Gx, ST72262Gx, ST72264Gx SERIAL COMMUNICATIONS INTERFACE (Cont’d) 11.5.4.7 Parity Control Parity control (generation of parity bit in transmis- sion and parity checking in reception) can be ena- bled by setting the PCE bit in the SCICR1 register. Depending on the ...
Page 95
SERIAL COMMUNICATIONS INTERFACE (Cont’d) 11.5.4.9 Clock Deviation Causes The causes which contribute to the total deviation are: – Deviation due to transmitter error (Local TRA oscillator error of the transmitter or the trans- mitter is transmitting at a ...
Page 96
ST72260Gx, ST72262Gx, ST72264Gx SERIAL COMMUNICATIONS INTERFACE (Cont’d) 11.5.5 Low Power Modes Mode Description No effect on SCI. WAIT SCI interrupts cause the device to exit from Wait mode. SCI registers are frozen. In Halt mode, the SCI stops transmit- HALT ...
Page 97
SERIAL COMMUNICATIONS INTERFACE (Cont’d) 11.5.7 Register Description STATUS REGISTER (SCISR) Read Only Reset Value: 1100 0000 (C0h) 7 TDRE TC RDRF IDLE OR Bit 7 = TDRE Transmit data register empty. This bit is set by hardware when the content ...
Page 98
ST72260Gx, ST72262Gx, ST72264Gx SERIAL COMMUNICATIONS INTERFACE (Cont’d) CONTROL REGISTER 1 (SCICR1) Read/Write Reset Value: x000 0000 (x0h SCID M WAKE Bit Receive data bit 8. This bit is used to store the 9th bit ...
Page 99
SERIAL COMMUNICATIONS INTERFACE (Cont’d) CONTROL REGISTER 2 (SCICR2) Read/Write Reset Value: 0000 0000 (00h) 7 TIE TCIE RIE ILIE TE Bit 7 = TIE Transmitter interrupt enable. This bit is set and cleared by software. 0: Interrupt is inhibited 1: ...
Page 100
ST72260Gx, ST72262Gx, ST72264Gx SERIAL COMMUNICATIONS INTERFACE (Cont’d) DATA REGISTER (SCIDR) Read/Write Reset Value: Undefined Contains the Received or Transmitted data char- acter, depending on whether it is read from or writ- ten to. 7 DR7 DR6 DR5 DR4 DR3 The ...
Page 101
SERIAL COMMUNICATIONS INTERFACE (Cont’d) EXTENDED RECEIVE PRESCALER DIVISION REGISTER (SCIERPR) Read/Write Reset Value: 0000 0000 (00h) Allows setting of the Extended Prescaler rate divi- sion factor for the receive circuit. 7 ERPR ERPR ERPR ERPR ERPR ...
Page 102
ST72260Gx, ST72262Gx, ST72264Gx SERIAL COMMUNICATIONS INTERFACE (Cont’d) Table 20. SCI Register Map and Reset Values Address Register Name (Hex.) SCISR 50 Reset Value SCIDR 51 Reset Value SCIBRR 52 Reset Value SCICR1 53 Reset Value SCICR2 54 Reset Value SCIERPR ...
Page 103
I C BUS INTERFACE (I2C) 11.6.1 Introduction 2 The I C Bus Interface serves as an interface be- tween the microcontroller and the serial I provides both multimaster and slave functions, 2 and controls all I C bus-specific ...
Page 104
ST72260Gx, ST72262Gx, ST72264Gx BUS INTERFACE (Cont’d) Acknowledge may be enabled and disabled by software. 2 The I C interface address and/or general call ad- dress can be selected by software. 2 The speed of the I C ...
Page 105
I C BUS INTERFACE (Cont’d) 11.6.4 Functional Description Refer to the CR, SR1 and SR2 registers in 11.6.7. for the bit definitions default the I C interface operates in Slave mode (M/SL bit is cleared) except when ...
Page 106
ST72260Gx, ST72262Gx, ST72264Gx INTERFACE (Cont’d) How to release the SDA / SCL lines Set and subsequently clear the STOP bit while BTF is set. The SDA/SCL lines are released after the transfer of the current byte. SMBus ...
Page 107
I C BUS INTERFACE (Cont’d) Master Transmitter Following the address transmission and after SR1 register has been read, the master sends bytes from the DR register to the SDA line via the inter- nal shift register. The master waits ...
Page 108
ST72260Gx, ST72262Gx, ST72264Gx BUS INTERFACE (Cont’d) Figure 59. Transfer Sequencing 7-bit Slave receiver: S Address A Data1 EV1 7-bit Slave transmitter: S Address A Data1 EV1 EV3 7-bit Master receiver: S Address A EV5 EV6 7-bit Master ...
Page 109
I C BUS INTERFACE (Cont’d) 11.6.5 Low Power Modes Mode 2 No effect interface. WAIT interrupts cause the device to exit from WAIT mode registers are frozen. 2 HALT In ...
Page 110
ST72260Gx, ST72262Gx, ST72264Gx BUS INTERFACE (Cont’d) 11.6.7 Register Description CONTROL REGISTER (CR) Read / Write Reset Value: 0000 0000 (00h ENGC START ACK Bit 7:6 = Reserved. Forced to 0 ...
Page 111
I C BUS INTERFACE (Cont’ STATUS REGISTER 1 (SR1) Read Only Reset Value: 0000 0000 (00h) 7 EVF ADD10 TRA BUSY BTF Bit 7 = EVF Event flag. This bit is set by hardware as soon ...
Page 112
ST72260Gx, ST72262Gx, ST72264Gx BUS INTERFACE (Cont’d) Bit 1 = M/SL Master/Slave. This bit is set by hardware as soon as the interface is in Master mode (writing START=1 cleared by hardware after detecting a Stop ...
Page 113
I C BUS INTERFACE (Cont’ CLOCK CONTROL REGISTER (CCR) Read / Write Reset Value: 0000 0000 (00h) 7 FM/SM CC6 CC5 CC4 CC3 Bit 7 = FM/SM Fast/Standard I This bit is set and cleared by ...
Page 114
ST72260Gx, ST72262Gx, ST72264Gx BUS INTERFACE (Cont’ OWN ADDRESS REGISTER (OAR1) Read / Write Reset Value: 0000 0000 (00h) 7 ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 7-bit Addressing Mode Bit 7:1 = ADD[7:1] ...
Page 115
I²C BUS INTERFACE (Cont’d) 2 Table 21 Register Map and Reset Values Address Register 7 Label (Hex.) I2CCR 0028h Reset Value 0 I2CSR1 EVF 0029h Reset Value 0 I2CSR2 002Ah Reset Value 0 I2CCCR FM/SM 02Bh Reset Value ...
Page 116
ST72260Gx, ST72262Gx, ST72264Gx 11.7 10-BIT A/D CONVERTER (ADC) 11.7.1 Introduction The on-chip Analog to Digital Converter (ADC) pe- ripheral is a 10-bit, successive approximation con- verter with internal sample and hold circuitry. This peripheral has 6 multiplexed analog input chan- ...
Page 117
A/D CONVERTER (ADC) (Cont’d) 11.7.3.2 Digital A/D Conversion Result The conversion is monotonic, meaning that the re- sult never decreases if the analog input does not and never increases if the analog input does not. If the input voltage ...
Page 118
ST72260Gx, ST72262Gx, ST72264Gx 10-BIT A/D CONVERTER (ADC) (Cont’d) 11.7.6 Register Description CONTROL/STATUS REGISTER (ADCCSR) Read/Write (Except bit 7 read only) Reset Value: 0000 0000 (00h) 7 EOC SPEED ADON SLOW 0 Bit 7 = EOC End of Conversion This bit ...
Page 119
A/D CONVERTER (ADC) (Cont’d) Table 23. ADC Register Map and Reset Values Address Register 7 Label (Hex.) ADCDRL 006Fh 0 Reset Value ADCDRH D9 0070h Reset Value 0 ADCCSR EOC 0071h Reset Value 0 ST72260Gx, ST72262Gx, ST72264Gx 6 5 ...
Page 120
ST72260Gx, ST72262Gx, ST72264Gx 12 INSTRUCTION SET 12.1 CPU ADDRESSING MODES The CPU features 17 different addressing modes which can be classified in 7 main groups: Addressing Mode Example Inherent nop Immediate ld A,#$55 Direct ld A,$55 Indexed ld A,($55,X) Indirect ...
Page 121
INSTRUCTION SET OVERVIEW (Cont’d) 12.1.1 Inherent All Inherent instructions consist of a single byte. The opcode fully specifies all the required informa- tion for the CPU to process the operation. Inherent Instruction NOP No operation TRAP S/W Interrupt Wait For ...
Page 122
ST72260Gx, ST72262Gx, ST72264Gx INSTRUCTION SET OVERVIEW (Cont’d) 12.1.6 Indirect Indexed (Short, Long) This is a combination of indirect and short indexed addressing modes. The operand is referenced by its memory address, which is defined by the un- signed addition of ...
Page 123
INSTRUCTION SET OVERVIEW (Cont’d) 12.2 INSTRUCTION GROUPS The ST7 family devices use an Instruction Set consisting of 63 instructions. The instructions may Load and Transfer Stack operation Increment/Decrement Compare and Tests Logical operations Bit Operation Conditional Bit Test and Branch ...
Page 124
ST72260Gx, ST72262Gx, ST72264Gx INSTRUCTION SET OVERVIEW (Cont’d) Mnemo Description ADC Add with Carry ADD Addition AND Logical And BCP Bit compare A, Memory BRES Bit Reset BSET Bit Set BTJF Jump if bit is false (0) BTJT Jump if bit ...
Page 125
INSTRUCTION SET OVERVIEW (Cont’d) Mnemo Description JRULE Jump Load MUL Multiply NEG Negate (2's compl) NOP No Operation OR OR operation POP Pop from the Stack PUSH Push onto the Stack RCF Reset ...
Page 126
ST72260Gx, ST72262Gx, ST72264Gx 13 ELECTRICAL CHARACTERISTICS 13.1 PARAMETER CONDITIONS Unless otherwise specified, all voltages are re- ferred 13.1.1 Minimum and Maximum values Unless otherwise specified the minimum and max- imum values are guaranteed in the worst ...
Page 127
ABSOLUTE MAXIMUM RATINGS Stresses above those listed as “absolute maxi- mum ratings” may cause permanent damage to the device. This is a stress rating only and func- tional operation of the device under these condi- 13.2.1 Voltage Characteristics Symbol ...
Page 128
ST72260Gx, ST72262Gx, ST72264Gx 13.3 OPERATING CONDITIONS 13.3.1 General Operating Conditions T = -40 to +85°C unless otherwise specified. A Symbol Parameter V Supply voltage DD External clock frequency on OSC1 f OSC pin Figure 64. f Maximum Operating Frequency Versus ...
Page 129
OPERATING CONDITIONS (Cont’d) 13.3.2 Operating Conditions with Low Voltage Detector (LVD -40 to +85°C unless otherwise specified A Symbol Parameter Reset release threshold V IT+(LVD) (V rise) DD Reset generation threshold V IT-(LVD) (V fall LVD ...
Page 130
ST72260Gx, ST72262Gx, ST72264Gx OPERATING CONDITIONS (Cont’d) 13.3.3 Auxiliary Voltage Detector (AVD) Thresholds T = -40 to +85°C unless otherwise specified A Symbol Parameter 1⇒0 AVDF flag toggle threshold V IT+(AVD) (V rise) DD 0⇒1 AVDF flag toggle threshold V IT-(AVD) ...
Page 131
SUPPLY CURRENT CHARACTERISTICS The following current consumption specified for the ST7 functional operating modes over temperature range does not take into account the clock source current consumption. To get the total device consump- tion, the two current values must ...
Page 132
ST72260Gx, ST72262Gx, ST72264Gx SUPPLY CURRENT CHARACTERISTICS (Cont’d) Figure 66. Typical I in RUN Fosc=16MHz 9 Fosc=8MHz 8 Fosc=4MHz 7 Fosc=2MHz 2.5 3 3.5 4 4.5 Vdd (V) Figure 67. ...
Page 133
SUPPLY CURRENT CHARACTERISTICS (Cont’d) 13.4.2 HALT and ACTIVE-HALT Modes Symbol Parameter Supply current in HALT mode I DD Supply current in ACTIVE-HALT mode 13.4.3 Supply and Clock Managers The previous current consumption specified for the ST7 functional operating modes over ...
Page 134
ST72260Gx, ST72262Gx, ST72264Gx SUPPLY CURRENT CHARACTERISTICS (Cont’d) 13.4.4 On-chip peripherals Symbol Parameter I 16-bit Timer supply current DD(TIM SPI supply current DD(SPI SCI supply current DD(SCI I2C supply current DD(I2C) I ADC supply current ...
Page 135
CLOCK AND TIMING CHARACTERISTICS Subject to general operating conditions for V 13.5.1 General Timings Symbol Parameter t Instruction cycle time c(INST) Interrupt reaction time t = ∆t v(IT v(IT) c(INST) 13.5.2 External Clock Source Symbol Parameter ...
Page 136
ST72260Gx, ST72262Gx, ST72264Gx CLOCK AND TIMING CHARACTERISTICS (Cont’d) 13.5.3 Crystal and Ceramic Resonator Oscillators The ST7 internal clock can be supplied with four different Crystal/Ceramic resonator oscillators. All the information given in this paragraph are based on characterization results with ...
Page 137
CLOCK AND TIMING CHARACTERISTICS (Cont’d) f OSC Supplier (MHz Notes: 1. Resonator characteristics given by the ceramic resonator manufacturer. 2. SMD = [-R0: Plastic tape package ( LEAD = [-A0: Flat pack package (Radial taping Ho= ...
Page 138
ST72260Gx, ST72262Gx, ST72264Gx CLOCK CHARACTERISTICS (Cont’d) 13.5.4 RC Oscillators The ST7 internal clock can be supplied with an in- ternal RC oscillator. Symbol Parameter Internal RC oscillator frequency f OSC (RCINT) See Figure 73 Figure 72. Typical Application with RC ...
Page 139
CLOCK CHARACTERISTICS (Cont’d) 13.5.5 PLL Characteristics Symbol Parameter V PLL Operating Range DD(PLL) f PLL input frequency range OSC ∆ Instantaneous PLL jitter CPU CPU Note: 1. Data characterized but not tested. Figure 74. PLL Jitter vs. Signal ...
Page 140
ST72260Gx, ST72262Gx, ST72264Gx 13.6 MEMORY CHARACTERISTICS 13.6.1 RAM and Hardware Registers Symbol Parameter V Data retention mode RM 13.6.2 XFlash Program Memory Symbol Parameter Operating voltage for Flash write erase Programming time for 1~32 bytes t prog Programming ...
Page 141
EMC CHARACTERISTICS Susceptibility tests are performed on a sample ba- sis during product characterization. 13.7.1 Functional EMS (Electro Magnetic Susceptibility) Based on a simple running application on the product (toggling 2 LEDs through I/O ports), the product is stressed ...
Page 142
ST72260Gx, ST72262Gx, ST72264Gx EMC CHARACTERISTICS (Cont’d) 13.7.2 Electro Magnetic Interference (EMI) Based on a simple application running on the product (toggling 2 LEDs through the I/O ports), the product is monitored in terms of emission. This emission test is in ...
Page 143
... Dynamic latch-up class Notes: 1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC spec- ifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the JEDEC criteria (international standard). ...
Page 144
ST72260Gx, ST72262Gx, ST72264Gx 13.8 I/O PORT PIN CHARACTERISTICS 13.8.1 General Characteristics T = -40 to +85°C unless otherwise specified A Symbol Parameter V Input low level voltage IL V Input high level voltage IH V Schmitt trigger voltage hysteresis hys ...
Page 145
I/O PORT PIN CHARACTERISTICS (Cont’d) Figure 77. Typical I vs 120 T=25C 100 T=-45C 80 T=90C 2.5 3 3.5 4 4.5 5 5.5 6 Vdd(V) Figure 78. Typical V IL 2.5 2 ...
Page 146
ST72260Gx, ST72262Gx, ST72264Gx I/O PORT PIN CHARACTERISTICS (Cont’d) 13.8.2 Output Driving Current T = -40 to +85°C unless otherwise specified A Symbol Parameter Output low level voltage for a standard I/O pin when 8 pins are sunk at same time ...
Page 147
I/O PORT PIN CHARACTERISTICS (Cont’d) Figure 80. Typ =5V (standard 1.8 1.6 T=25C 1.4 T=90C 1.2 1 T=-45C 0.8 0.6 0.4 0 Iio(mA) Figure 81. Typ ...
Page 148
ST72260Gx, ST72262Gx, ST72264Gx I/O PORT PIN CHARACTERISTICS (Cont’d) Figure 84. Typ =2. 2.5 2 T=25C 1.5 T=90C 1 T=-45C 0 0.5 1 Iio(mA) Figure 85. Typ = ...
Page 149
I/O PORT PIN CHARACTERISTICS (Cont’d) Figure 88. Typical V vs 0.6 0.5 0.4 0.3 0.2 0.1 0.0 2.5 3 3.5 4 Vdd (V) Figure 89. Typical V vs 0.6 0.5 0.4 0.3 0.2 0.1 0.0 2.4 ...
Page 150
ST72260Gx, ST72262Gx, ST72264Gx 13.9 CONTROL PIN CHARACTERISTICS 13.9.1 Asynchronous RESET Pin T = -40 to +85°C unless otherwise specified A Symbol Parameter V Input low level voltage IL V Input high level voltage IH V Schmitt trigger voltage hysteresis hys ...
Page 151
CONTROL PIN CHARACTERISTICS (Cont’d) Figure 91. RESET pin protection when LVD is enabled. Required EXTERNAL RESET 0.01µF Figure 92. RESET pin protection when LVD is disabled. Recommended for EMC V DD 0.01µF USER EXTERNAL RESET CIRCUIT 0.01µF Required Note 1: ...
Page 152
ST72260Gx, ST72262Gx, ST72264Gx 13.10 TIMER PERIPHERAL CHARACTERISTICS Subject to general operating conditions for and T unless otherwise specified. OSC A Refer to I/O port characteristics for more details on the input/output alternate function characteristics (output compare, input ...
Page 153
COMMUNICATION INTERFACE CHARACTERISTICS 13.11.1 SPI - Serial Peripheral Interface Subject to general operating conditions for and T unless otherwise specified. OSC A Symbol Parameter f SCK SPI clock frequency 1/t c(SCK) t r(SCK) SPI clock rise ...
Page 154
ST72260Gx, ST72262Gx, ST72264Gx COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d) Figure 94. SPI Slave Timing Diagram with CPHA=1 SS INPUT t su(SS) CPHA=0 CPOL=0 CPHA=0 CPOL=1 t w(SCKH) t a(SO) t w(SCKL) see MISO OUTPUT HZ note 2 t su(SI) MOSI INPUT Figure ...
Page 155
COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d) 2 13.11 Inter IC Control Interface Subject to general operating conditions for and T unless otherwise specified. OSC A Refer to I/O port characteristics for more details on the input/output ...
Page 156
ST72260Gx, ST72262Gx, ST72264Gx COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d) The following table gives the values to be written in the I2CCCR register to obtain the required I SCL line frequency. Table 26. SCL Frequency Table f SCL V = 3.3 V (kHz) ...
Page 157
ADC CHARACTERISTICS V = 2.7 to 5.5V -40°C to 85°C, unless otherwise specified DD A Symbol Parameter f ADC clock frequency ADC V Conversion voltage range AIN C Internal sample and hold capacitor ADC t Conversion ...
Page 158
ST72260Gx, ST72262Gx, ST72264Gx ADC CHARACTERISTICS (Cont’d) 13.12.0.1 General PCB Design Guidelines To obtain best results, some general design and layout rules should be followed when designing the application PCB to shield the noise-sensitive, analog physical interface from noise generating CMOS ...
Page 159
PACKAGE CHARACTERISTICS 14.1 PACKAGE MECHANICAL DATA Figure 101. 32-Pin Plastic Dual In-Line Package, Shrink 400-mil Width Figure 102. Figure 103. 28-Pin Plastic Small Outline Package, 300-mil Width D B ST72260Gx, ST72262Gx, ST72264Gx ...
Page 160
ST72260Gx, ST72262Gx, ST72264Gx Figure 104. Low Profile Fine Pitch Ball Grid Array Package SEATING PLANE C A1 CORNER INDEX AREA (SEE NOTE 3) 14.2 THERMAL CHARACTERISTICS Symbol Package thermal resistance (junction to ambient) R thJA P Power dissipation D T ...
Page 161
... LEAD-FREE PACKAGE INFORMATION STMicroelectronics is fully committed to Environ- ment protection and sustainable development and started in 1997 a volontary program for removing polluting and hazardous substances from all de- vices. In 2000, a strategic program, named ECO- PACK®, has been officially launched to develop and implement solutions leading to environment ...
Page 162
ST72260Gx, ST72262Gx, ST72264Gx 15 DEVICE CONFIGURATION AND ORDERING INFORMATION Each device is available for production in user pro- grammable versions (FLASH) as well as in factory coded versions (ROM/FASTROM). ST7226x devices are ROM versions. ST72P26x devices are Factory Advanced Service ...
Page 163
DEVICE CONFIGURATION (Cont’d) OPT 0 = FMP_W FLASH write protection This option indicates if the FLASH program mem- ory is write protected. Warning: When this option is selected, the pro- gram memory (and the option bit itself) can never be ...
Page 164
... Table 28. Supported Part Numbers Program Memory Part Number ST72F264G1B6 ST72F264G1M6 4K FLASH ST72F262G1B6 ST72F262G1M6 ST72F264G2B6 ST72F264G2M6 ST72F264G2H1 8K FLASH ST72F264G2H6E ST72F262G2B6 ST72F262G2M6 ST72F262G1B6 ST72F262G1M6 4K FLASH ST72F260G1B6 ST72F260G1M6 ST72P264G2B6/xxx ST72P264G2M6/xxx ST72P264G2H1/xxx 8K FASTROM ST72P262G2B6/xxx ST72P262G2M6/xxx ST72P262G1B6/xxx ST72P262G1M6/xxx 4K FASTROM ST72P260G1B6/xxx ST72P260G1M6/xxx ST72264G2B6/xxx ST72264G2M6/xxx ST72262G2B6/xxx ST72262G2M6/xxx ST72262G1B6/xxx ST72262G1M6/xxx ST72260G1B6/xxx ...
Page 165
... Reference /ROM or FASTROM Code* ROM or FASTROM code is assigned by STMicroelectronics. Code must be sent in .S19 format. .Hex extension cannot be processed. ...
Page 166
... ST72260Gx, ST72262Gx, ST72264Gx 15.3 DEVELOPMENT TOOLS STMicroelectronics offers a range of hardware and software development tools for the ST7 micro- controller family. Full details of tools available for the ST7 from third party manufacturers can be ob- tained from the STMicroelectronics Internet site: http//www.st.com. ...
Page 167
PACKAGE/SOCKET FOOTPRINT PROPOSAL Table 30. Suggested List of SDIP32 Socket Types Package / Probe SDIP32 TEXTOOL EMU PROBE Table 31. Suggested List of SO28 Socket Types Package / Probe SO28 YAMAICHI EMU PROBE Adapter from SO28 to SDIP32 footprint ...
Page 168
ST72260Gx, ST72262Gx, ST72264Gx 16 KNOWN LIMITATIONS 16.1 ALL FLASH AND ROM DEVICES 16.1.1 16-bit timer PWM Mode In PWM mode, the first PWM pulse is missed after writing the value FFFCh in the OC12R register.In PWM mode, the first PWM ...
Page 169
I/O Port B and C configuration When using an external quartz crystal or ceramic resonator, the f clock may be disturbed be- OSC2 cause the device goes into reserved mode control- led by Port B and C. This happens ...
Page 170
ST72260Gx, ST72262Gx, ST72264Gx bit) accuracy does not meet the accuracy specified in the data sheet. Workaround In order to have the accuracy specified in the da- tasheet, the first conversion after a ADC switch-on has to be ignored. 16.2.11 Negative ...
Page 171
REVISION HISTORY Table 33. Revision History Date Rev. Added “SMBus V1.1 Compliant” for I²C on page 1 Added one note in Added SMBus compatibility information in Section 11.6.4.1 on page 105 Changed note 1 in Added note 3 in ...
Page 172
... No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics ...