STM32F101RBT6 STMicroelectronics, STM32F101RBT6 Datasheet - Page 52

MCU ARM 128KB FLASH/TIMER 64LQFP

STM32F101RBT6

Manufacturer Part Number
STM32F101RBT6
Description
MCU ARM 128KB FLASH/TIMER 64LQFP
Manufacturer
STMicroelectronics
Series
STM32r
Datasheets

Specifications of STM32F101RBT6

Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
36MHz
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
DMA, PDR, POR, PVD, PWM, Temp Sensor, WDT
Number Of I /o
51
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Processor Series
STM32F101x
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
16 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
36 MHz
Number Of Programmable I/os
64
Number Of Timers
3 x 16 bit
Operating Supply Voltage
2 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWARM, EWARM-BL, MDK-ARM, RL-ARM, ULINK2
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 16 Channel
For Use With
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Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
497-6059

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Electrical characteristics
5.3.11
5.3.12
52/85
Absolute maximum ratings (electrical sensitivity)
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the JESD22-A114/C101 standard.
Table 31.
1. Based on characterization results, not tested in production.
Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
These tests are compliant with EIA/JESD 78 IC latch-up standard.
Table 32.
I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in
performed under the conditions summarized in
compliant.
V
V
Symbol
Symbol
ESD(HBM)
ESD(CDM)
LU
A supply overvoltage is applied to each power supply pin
A current injection is applied to each input, output and configurable I/O pin
Static latch-up class
Electrostatic discharge
voltage (human body model)
Electrostatic discharge
voltage (charge device model)
ESD absolute maximum ratings
Electrical sensitivities
Parameter
Ratings
Doc ID 13586 Rev 13
T
A
+85 °C conforming to JESD78A
T
conforming to JESD22-A114
T
conforming to JESD22-C101
A
A
+25 °C
+25 °C
Table
Conditions
Conditions
Table 33
8. All I/Os are CMOS and TTL
STM32F101x8, STM32F101xB
are derived from tests
Class
2
II
Maximum
value
2000
500
II level A
Class
(1)
Unit
V

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