C8051T600-GS Silicon Laboratories Inc, C8051T600-GS Datasheet
C8051T600-GS
Specifications of C8051T600-GS
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C8051T600-GS Summary of contents
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... Built-in voltage supply monitor Temperature Range: –40 to +85 °C Package Options QFN11 - QFN10 (C8051T606 Only) - MSOP10 (C8051T606 Only) - SOIC14 (C8051T600/1/2/3/4/5 Only) PERIPHERALS C8051T600/2/4 1.5/2/4/8kB EPROM INTERRUPTS Rev. 1.2 3/09 This information applies to a product under development. Its characteristics and specifications are subject to change without notice. ...
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... Tracking Modes......................................................................................... 42 9.3.3. Settling Time Requirements...................................................................... 43 9.4. Programmable Window Detector....................................................................... 47 9.4.1. Window Detector Example........................................................................ 49 9.5. ADC0 Analog Multiplexer (C8051T600/2/4 only)............................................... 50 10. Temperature Sensor (C8051T600/2/4 only) ......................................................... 52 10.1. Calibration ....................................................................................................... 52 11. Voltage Reference Options ................................................................................... 55 12. Voltage Regulator (REG0) ..................................................................................... 57 13. Comparator0........................................................................................................... 59 13.1. Comparator Multiplexer ................................................................................... 63 14 ...
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... Priority Crossbar Decoder ............................................................................. 111 22.4. Port I/O Initialization ...................................................................................... 114 22.5. Special Function Registers for Accessing and Configuring Port I/O ............. 118 23. SMBus................................................................................................................... 120 23.1. Supporting Documents .................................................................................. 121 23.2. SMBus Configuration..................................................................................... 121 23.3. SMBus Operation .......................................................................................... 121 23.3.1. Transmitter Vs. Receiver....................................................................... 122 C8051T600/1/2/3/4/5/6 Rev. 1.2 3 ...
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... C8051T600/1/2/3/4/5/6 23.3.2. Arbitration.............................................................................................. 122 23.3.3. Clock Low Extension............................................................................. 122 23.3.4. SCL Low Timeout.................................................................................. 122 23.3.5. SCL High (SMBus Free) Timeout ......................................................... 123 23.4. Using the SMBus........................................................................................... 123 23.4.1. SMBus Configuration Register.............................................................. 123 23.4.2. SMB0CN Control Register .................................................................... 127 23.4.3. Data Register ........................................................................................ 130 23.5. SMBus Transfer Modes................................................................................. 131 23 ...
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... C2 Pin Sharing .............................................................................................. 185 Document Change List.............................................................................................. 186 Contact Information................................................................................................... 188 C8051T600/1/2/3/4/5/6 Rev. 1.2 5 ...
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... Figure 1.3. C8051T606 Block Diagram ................................................................... 15 2. Ordering Information 3. Pin Definitions Figure 3.1. C8051T600/1/2/3/4/5-GM QFN11 Pinout Diagram (Top View) ............. 19 Figure 3.2. C8051T600/1/2/3/4/5-GS SOIC14 Pinout Diagram (Top View) ............ 19 Figure 3.3. C8051T606-GM QFN11 Pinout Diagram (Top View) ............................ 20 Figure 3.4. C8051T606-GT MSOP10 Pinout Diagram (Top View) .......................... 20 Figure 3 ...
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... Figure 24.5. 9-Bit UART Timing Diagram .............................................................. 140 Figure 24.6. UART Multi-Processor Mode Interconnect Diagram ......................... 141 25. Timers Figure 25.1. T0 Mode 0 Block Diagram ................................................................. 148 Figure 25.2. T0 Mode 2 Block Diagram ................................................................. 149 Figure 25.3. T0 Mode 3 Block Diagram ................................................................. 150 Figure 25.4. Timer 2 16-Bit Mode Block Diagram ................................................. 155 C8051T600/1/2/3/4/5/6 Rev. 1.2 7 ...
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... C8051T600/1/2/3/4/5/6 Figure 25.5. Timer 2 8-Bit Mode Block Diagram ................................................... 156 26. Programmable Counter Array Figure 26.1. PCA Block Diagram ........................................................................... 160 Figure 26.2. PCA Counter/Timer Block Diagram ................................................... 161 Figure 26.3. PCA Interrupt Block Diagram ............................................................ 162 Figure 26.4. PCA Capture Mode Diagram ............................................................. 164 Figure 26.5. PCA Software Timer Mode Diagram ................................................. 165 Figure 26 ...
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... System Overview 2. Ordering Information Table 2.1. Product Selection Guide ......................................................................... 16 3. Pin Definitions Table 3.1. Pin Definitions for the C8051T600/1/2/3/4/5 ........................................... 17 Table 3.2. Pin Definitions for the C8051T606 .......................................................... 18 4. QFN-11 Package Specifications Table 4.1. QFN-11 Package Dimensions ................................................................ 22 Table 4.2. QFN-11 PCB Land Pattern Dimensions ................................................. 23 5 ...
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... C8051T600/1/2/3/4/5/6 18. Power Management Modes 19. Reset Sources 20. EPROM Memory Table 20.1. Security Byte Decoding ........................................................................ 98 21. Oscillators and Clock Selection 22. Port Input/Output Table 22.1. Port I/O Assignment for Analog Functions ......................................... 109 Table 22.2. Port I/O Assignment for Digital Functions ........................................... 109 Table 22.3. Port I/O Assignment for External Digital Event Capture Functions .... 110 23 ...
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... SFR Definition 23.1. SMB0CF: SMBus Clock/Configuration ...................................... 126 SFR Definition 23.2. SMB0CN: SMBus Control .......................................................... 128 SFR Definition 23.3. SMB0DAT: SMBus Data ............................................................ 130 SFR Definition 24.1. SCON0: Serial Port 0 Control .................................................... 142 SFR Definition 24.2. SBUF0: Serial (UART0) Port Data Buffer .................................. 143 C8051T600/1/2/3/4/5/6 Rev. 1.2 11 ...
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... C8051T600/1/2/3/4/5/6 SFR Definition 25.1. CKCON: Clock Control .............................................................. 146 SFR Definition 25.2. TCON: Timer Control ................................................................. 151 SFR Definition 25.3. TMOD: Timer Mode ................................................................... 152 SFR Definition 25.4. TL0: Timer 0 Low Byte ............................................................... 153 SFR Definition 25.5. TL1: Timer 1 Low Byte ............................................................... 153 SFR Definition 25.6. TH0: Timer 0 High Byte ............................................................. 154 SFR Definition 25 ...
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... User software has complete control of all peripherals and may individually shut down any or all peripherals for power savings. Code written for the C8051T600/1/2/3/4/5/6 family of processors will run on the C8051F300 Mixed-Signal ISP Flash microcontroller, providing a quick, cost-effective way to develop code without requiring special emulator circuitry. The C8051T600/1/2/3/4/5/6 processors include Silicon Laboratories’ ...
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... SRAM Programming Hardware SYSCLK C2D Power Net VDD External GND EXTCLK Clock Circuit System Clock Configuration Figure 1.1. C8051T600/2/4 Block Diagram CIP-51 8051 Controller Core 2k/4k/8k Byte Power On EPROM Program Reset Memory Reset Debug / C2CK/RST 256 byte SRAM Programming Hardware ...
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... Byte SRAM Programming Hardware SYSCLK C2D Power Net VDD External GND EXTCLK Clock Circuit System Clock Configuration Figure 1.3. C8051T606 Block Diagram C8051T600/1/2/3/4/5/6 Port I/O Configuration Digital Peripherals UART Timers 0, 1, and 2 Priority Crossbar Decoder PCA/ WDT SFR SMBus Bus Crossbar Control ...
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... C8051T600/1/2/3/4/5/6 2. Ordering Information Table 2.1. Product Selection Guide 1 C8051T600- C8051T600- C8051T601- C8051T601- C8051T602- C8051T602- C8051T603- C8051T603- C8051T604- C8051T604- C8051T605- C8051T605- C8051T606-GM 25 1.5k C8051T606-GT 25 1.5k C8051T606-ZM 25 1.5k Notes: 1. 512 Bytes Reserved 2. Lead Finish is 100% Matte Tin (Sn) 16 256 256 256 — — ...
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... Pin Definitions Table 3.1. Pin Definitions for the C8051T600/1/2/3/4/5 Name QFN11 SOIC14 Type Pin Pin GND 11 3 RST / I/O C2CK D I I/O C2D P0 I VREF EXTCLK CNVSTR — 4,9,11 C8051T600/1/2/3/4/5/6 Description Power Supply Voltage. ...
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... C8051T600/1/2/3/4/5/6 Table 3.2. Pin Definitions for the C8051T606 Name QFN11 MSOP10 QFN10 Pin Pin Pin GND GND* 11 — — RST / C2CK P0 C2D EXTCLK P0 P0 Type Description Power Supply Voltage. Ground (Required). Ground (Optional). D I/O Device Reset. Open-drain output of internal POR or V monitor ...
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... P0.0 / VREF P0.3 / EXTCLK 5 Figure 3.1. C8051T600/1/2/3/4/5-GM QFN11 Pinout Diagram (Top View) P0.6 / CNVSTR 1 P0.7 / C2D 2 GND P0.0 / VREF 5 P0 Figure 3.2. C8051T600/1/2/3/4/5-GS SOIC14 Pinout Diagram (Top View) C8051T600/1/2/3/4/5/6 TOP VIEW 10 P0.7 / C2D P0 CNVSTR 11 RST / C2CK 8 GND P0.5 7 P0.4 6 TOP VIEW ...
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... C8051T600/1/2/3/4 P0.3 / EXTCLK 5 Figure 3.3. C8051T606-GM QFN11 Pinout Diagram (Top View P0 P0 P0.3 / EXTCLK 5 Figure 3.4. C8051T606-GT MSOP10 Pinout Diagram (Top View) 20 TOP VIEW 10 P0.7 / C2D GND 9 11 GND* RST / C2CK 8 (Optional) P0.5 7 P0.4 6 TOP VIEW 10 P0.7 / C2D GND 9 8 RST / C2CK P0 ...
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... P0 TOP VIEW P0 P0.3 / EXTCLK 4 Figure 3.5. C8051T606-ZM QFN10 Pinout Diagram (Top View) C8051T600/1/2/3/4/5/6 NC P0.7 / C2D 9 10 GND 8 RST / C2CK 7 5 P0.5 6 P0.4 Rev. 1.2 21 ...
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... C8051T600/1/2/3/4/5/6 4. QFN-11 Package Specifications Figure 4.1. QFN-11 Package Drawing Table 4.1. QFN-11 Package Dimensions Dimension Min Nom A 0.80 0.90 A1 0.03 0.07 A3 0.25 REF b 0.18 0.25 D 3.00 BSC D2 1.30 1.35 e 0.50 BSC Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. ...
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... The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pins array of 1.30 x 0.60 mm openings on 0.80 mm pitch should be used for the center pad. Card Assembly 8. A No-Clean, Type-3 solder paste is recommended. 9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. C8051T600/1/2/3/4/5/6 Dimension Min X2 1. ...
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... C8051T600/1/2/3/4/5/6 5. SOIC-14 Package Specifications Figure 5.1. SOIC-14 Package Drawing Table 5.1. SOIC-14 Package Dimensions Dimension Min Nom A — — A1 0.10 — b 0.33 — c 0.17 — D 8.65 BSC E 6.00 BSC E1 3.90 BSC e 1.27 BSC Notes: 1. All dimensions shown are in millimeters (mm). 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. ...
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... The stencil thickness should be 0.125 mm (5 mils). 6. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads. Card Assembly 7. A No-Clean, Type-3 solder paste is recommended. 8. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. C8051T600/1/2/3/4/5/6 Dimension Min X1 0. ...
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... C8051T600/1/2/3/4/5/6 6. MSOP-10 Package Specifications Figure 6.1. MSOP-10 Package Drawing Table 6.1. MSOP-10 Package Dimensions Dimension Min Nom A — — A1 0.00 — A2 0.75 0.85 b 0.17 — c 0.08 — D 3.00 BSC E 4.90 BSC E1 3.00 BSC Notes: 1. All dimensions shown are in millimeters (mm). 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. ...
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... The stencil thickness should be 0.125 mm (5 mils). 8. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads. Card Assembly 9. A No-Clean, Type-3 solder paste is recommended. 10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. C8051T600/1/2/3/4/5/6 Dimension Min X1 — ...
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... C8051T600/1/2/3/4/5/6 7. QFN-10 Package Specifications Figure 7.1. QFN-10 Package Drawing Table 7.1. QFN-10 Package Dimensions Dimension Min Nom A 0.70 0.75 A1 0.00 — b 0.18 0.25 D 2.00 BSC. e 0.50 BSC. E 2.00 BSC. Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. ...
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... The stencil thickness should be 0.125 mm (5 mils). 8. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads. Card Assembly 9. A No-Clean, Type-3 solder paste is recommended. 10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. C8051T600/1/2/3/4/5/6 Dimension Min X1 0.20 Y1 ...
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... C8051T600/1/2/3/4/5/6 8. Electrical Characteristics 8.1. Absolute Maximum Specifications Table 8.1. Absolute Maximum Ratings Parameter Ambient temperature under bias Storage temperature Voltage on RST or any Port I/O pin (except V during programming) with PP respect to GND Voltage on V with respect to GND PP during a programming operation Duration of High-voltage on V ...
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... C8051T600/1/2/3/4/5 Digital Sup- ply Current with CPU Active C8051T600/1/2/3/4/5 Digital Sup- ply Current with CPU Inactive (not accessing EPROM) C8051T600/1/2/3/4/5 Digital Sup- ply Current (shutdown) C8051T606 Digital Supply Current with CPU Active C8051T606 Digital Supply Current with CPU Inactive (not accessing ...
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... C8051T600/1/2/3/4/5/6 Table 8.2. Global Electrical Characteristics –40 to +85 °C, 25 MHz system clock unless otherwise specified. Parameter Tsysl (SYSCLK low time) Tsysh (SYSCLK high time) Notes: 1. Analog performance is not guaranteed when V 2. SYSCLK must be at least 32 kHz to enable debugging. 3. Supply current parameters specified with Memory Power Controller enabled. ...
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... Port I/O push-pull –10 mA, Port I/O push-pull OH Output Low Voltage µ Input High Voltage Input Low Voltage Input Leakage Weak Pullup Off Current Weak Pullup On, V C8051T600/1/2/3/4/5/6 Conditions Min 0.1 DD — — — — 0 — – — IN Rev. 1.2 ...
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... Normal Mode Table 8.6. EPROM Electrical Characteristics Parameter EPROM Size C8051T600/1 C8051T602/3 C8051T604/5 C8051T606 Write Cycle Time (per Byte) Programming Voltage (V ) C8051T600/1/2/3/4/5 PP Programming Voltage (V ) C8051T606 PP Note: 512 bytes at location 0x1E00 to 0x1FFF are not available for program storage 34 Conditions Min = 8.5 mA, ...
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... Note: Represents one standard deviation from the mean. Table 8.9. Voltage Reference Electrical Characteristics V = 3.0 V; –40 to +85 °C unless otherwise specified. DD Parameter Input Voltage Range Input Current Sample Rate = 500 ksps; VREF = 2.5 V C8051T600/1/2/3/4/5/6 Conditions Min Typ 24 24.5 = 3.0 V, — 450 DD — ...
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... C8051T600/1/2/3/4/5/6 Table 8.10. ADC0 Electrical Characteristics V = 3.0 V, VREF = 2.40 V (REFSL=0), –40 to +85 °C unless otherwise specified. DD Parameter DC Accuracy Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Full Scale Error Offset Temperature Coefficient Dynamic performance (10 kHz sine-wave single-ended input below Full Scale, 500 ksps) ...
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... Inverting or Non-Inverting Input Voltage Range Input Offset Voltage Power Specifications Power Supply Rejection Powerup Time Supply Current at DC Mode 0 Mode 1 Mode 2 Mode 3 Note: Vcm is the common-mode voltage on CP0+ and CP0–. C8051T600/1/2/3/4/5/6 Conditions Min Typ — 240 — 240 — 400 — 400 — ...
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... C8051T600/1/2/3/4/5/6 8.3. Typical Performance Curves 6.0 5.0 4.0 3.0 2.0 1.0 0 Figure 8.1. C8051T600/1/2/3/4/5 Normal Mode Supply Current vs. Frequency 6.0 5.0 4.0 3.0 2.0 1.0 0 Figure 8.2. C8051T606 Normal Mode Supply Current vs. Frequency (MPCE = > SYSCLK (MHz) (MPCE = > SYSCLK (MHz) Rev ...
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... Figure 8.3. C8051T600/1/2/3/4/5 Idle Mode Supply Current vs. Frequency 2.0 1.5 1.0 0.5 0 Figure 8.4. C8051T606 Idle Mode Digital Current vs. Frequency (MPCE = 1) C8051T600/1/2/3/4/5/6 V > SYSCLK (MHz) (MPCE = 1) V > SYSCLK (MHz) Rev. 1 ...
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... The ADC is fully configurable under software control via Special Function Registers. The ADC may be con- figured to measure various different signals using the analog multiplexer described in Section “9.5. ADC0 Analog Multiplexer (C8051T600/2/4 only)” on page 50. The voltage reference for the ADC is selected as described in Section “11. Voltage Reference Options” on page 55. The ADC0 subsystem is enabled only when the AD0EN bit in the ADC0 Control register (ADC0CN) is set to logic 1 ...
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... Important Note About Using CNVSTR: The CNVSTR input pin also functions as a Port I/O pin. When the CNVSTR input is used as the ADC0 conversion source, the associated pin should be skipped by the Digi- tal Crossbar. See Section “22. Port Input/Output” on page 106 for details on Port I/O configuration. C8051T600/1/2/3/4/5/6 Left-Justified ADC0H:ADC0L (AD0LJST = 1) ...
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... C8051T600/1/2/3/4/5/6 9.3.2. Tracking Modes The AD0TM bit in register ADC0CN enables "delayed conversions", and will delay the actual conversion start by three SAR clock cycles, during which time the ADC will continue to track the input. If AD0TM is left at logic 0, a conversion will begin immediately, without the extra tracking time. For internal start-of-conver- sion sources, the ADC will track anytime it is not performing a conversion ...
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... R is the sum of the AMUX0 resistance and any external source resistance. TOTAL n is the ADC resolution in bits (10). Input Pin Note: See electrical specification tables for R Figure 9.3. ADC0 Equivalent Input Circuits C8051T600/1/2/3/4/5/6 n 2 ------ - ln ...
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... C8051T600/1/2/3/4/5/6 SFR Definition 9.1. ADC0CF: ADC0 Configuration Bit 7 6 AD0SC[4:0] Name Type 1 1 Reset SFR Address = 0xBC Bit Name 7:3 AD0SC[4:0] ADC0 SAR Conversion Clock Period Bits. SAR Conversion clock is derived from system clock by the following equation, where AD0SC refers to the 5-bit value held in bits AD0SC4–0. SAR Conversion clock requirements are given in the ADC specification table ...
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... For AD0LJST = 0: Bits 7–0 are the lower 8 bits of the 10-bit Data Word. For AD0LJST = 1: Bits 7–6 are the lower 2 bits of the 10-bit Data Word. Bits 5–0 will read 000000b. Note: In 8-bit mode AD0LJST is ignored, and ADC0L will read back 00000000b. C8051T600/1/2/3/4/5 ...
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... C8051T600/1/2/3/4/5/6 SFR Definition 9.4. ADC0CN: ADC0 Control Bit 7 6 AD0EN AD0TM AD0INT Name R/W R/W Type 0 0 Reset SFR Address = 0xE8; Bit-Addressable Bit Name 7 AD0EN ADC0 Enable Bit. 0: ADC0 Disabled. ADC0 is in low-power shutdown. 1: ADC0 Enabled. ADC0 is active and ready for data conversions. ...
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... ADC0GTH[7:0] ADC0 Greater-Than Data Word High-Order Bits. SFR Definition 9.6. ADC0GTL: ADC0 Greater-Than Data Low Byte Bit 7 6 Name Type 1 1 Reset SFR Address = 0xC3 Bit Name 7:0 ADC0GTL[7:0] ADC0 Greater-Than Data Word Low-Order Bits. C8051T600/1/2/3/4/5 ADC0GTH[7:0] R Function ADC0GTL[7:0] R/W ...
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... C8051T600/1/2/3/4/5/6 SFR Definition 9.7. ADC0LTH: ADC0 Less-Than Data High Byte Bit 7 6 Name Type 0 0 Reset SFR Address = 0xC6 Bit Name 7:0 ADC0LTH[7:0] ADC0 Less-Than Data Word High-Order Bits. SFR Definition 9.8. ADC0LTL: ADC0 Less-Than Data Low Byte Bit 7 6 Name ...
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... VREF x (128/1024) 0x2000 ADC0LTH:ADC0LTL 0x1FC0 0x1040 VREF x (64/1024) 0x1000 ADC0GTH:ADC0GTL 0x0FC0 AD0WINT not affected 0x0000 0 Figure 9.5. ADC Window Compare Example: Left-Justified Data C8051T600/1/2/3/4/5/6 window comparisons for right-justified ADC0H:ADC0L Input Voltage (AIN - GND) VREF x (1023/ 0x03FF 1024) 0x0081 VREF x (128/1024) 0x0080 ...
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... C8051T600/1/2/3/4/5/6 9.5. ADC0 Analog Multiplexer (C8051T600/2/4 only) ADC0 on the C8051T600/2/4 uses an analog input multiplexer to select the positive input to the ADC. Any of the following may be selected as the positive input: Port 0 I/O pins, the on-chip temperature sensor, or the positive power supply (V ). The ADC0 input channel is selected in the AMX0SL register described in DD SFR Definition 9 ...
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... Bit Name 7:4 Unused Unused. Read = 1000b; Write = Don’t Care. 3:0 AMX0P[3:0] AMUX0 Positive Input Selection. 0000: 0001: 0010: 0011: 0100: 0101: 0110: 0111: 1000: 1001: 1010 – 1111: C8051T600/1/2/3/4/5 R/W R Function P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 ...
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... C8051T600/1/2/3/4/5/6 10. Temperature Sensor (C8051T600/2/4 only) An on-chip temperature sensor is included on the C8051T600/2/4, which can be directly accessed via the ADC multiplexer. To use the ADC to measure the temperature sensor, the ADC mux channel should be configured to connect to the temperature sensor. The temperature sensor transfer function is shown in Figure 10 ...
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... Figure 10.2. Temperature Sensor Error with 1-Point Calibration at 0 °C C8051T600/1/2/3/4/5/6 20.00 40.00 Temperature (degrees C) Rev. 1.2 5.00 4.00 3.00 2.00 1.00 0.00 60.00 80.00 -1.00 -2.00 -3 ...
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... C8051T600/1/2/3/4/5/6 SFR Definition 10.1. TOFFH: Temperature Offset Measurement High Byte Bit 7 6 Name Type Varies Varies Reset SFR Address = 0xA3 Bit Name 7:0 TOFF[9:2] Temperature Sensor Offset High Order Bits. The temperature sensor offset registers represent the output of the ADC when mea- suring the temperature sensor at 0 ° ...
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... VDD External Voltage Reference R1 Circuit VREF GND + 4.7F 0.1F Recommended Bypass Capacitors Figure 11.1. Voltage Reference Functional Block Diagram C8051T600/1/2/3/4/5 the regulated 1.8 V internal supply (see DD REF0CN EN Temp Sensor 0 0 VDD 1 Internal 1 Regulator REGOVR Rev. 1.2 ...
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... C8051T600/1/2/3/4/5/6 SFR Definition 11.1. REF0CN: Reference Control Bit 7 6 Name R R Type 0 0 Reset SFR Address = 0xD1 Bit Name 7:5 Unused Unused. Read = 000b; Write = Don’t Care. 4 REGOVR Regulator Reference Override. This bit “overrides” the REFSL bit, and allows the internal regulator to be used as a ref- erence source ...
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... Voltage Regulator (REG0) C8051T600/1/2/3/4/5/6 devices include an internal voltage regulator (REG0) to regulate the internal core supply to 1.8 V from a V supply of 1.8 to 3.6 V. Two power-saving modes are built into the regulator to DD help reduce current consumption in low-power applications. These modes are accessed through the REG0CN register (SFR Definition 12 ...
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... C8051T600/1/2/3/4/5/6 SFR Definition 12.1. REG0CN: Voltage Regulator Control Bit 7 6 STOPCF BYPASS Name R/W R/W Type 0 0 Reset SFR Address = 0xC7 Bit Name 7 STOPCF Stop Mode Configuration. This bit configures the regulator’s behavior when the device enters STOP mode. 0: Regulator is still active in STOP mode. Any enabled reset source will reset the device ...
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... Comparator0 C8051T600/1/2/3/4/5/6 devices include an on-chip programmable voltage comparator, Comparator0, shown in Figure 13.1. The Comparator offers programmable response time and hysteresis, an analog input multiplexer, and two outputs that are optionally available at the Port pins: a synchronous “latched” output (CP0 asyn- chronous “raw” output (CP0A). The asynchronous CP0A signal is available even when the system clock is not active ...
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... C8051T600/1/2/3/4/5/6 externally driven from –0. trical specifications are given in Section “8. Electrical Characteristics” on page 30. The Comparator response time may be configured in software via the CPT0MD register (see SFR Defini- tion 13.2). Selecting a longer response time reduces the Comparator supply current. CP0+ ...
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... CP0HYP[1:0] Comparator0 Positive Hysteresis Control Bits. 00: Positive Hysteresis Disabled. 01: Positive Hysteresis = 5 mV. 10: Positive Hysteresis = 10 mV. 11: Positive Hysteresis = 20 mV. 1:0 CP0HYN[1:0] Comparator0 Negative Hysteresis Control Bits. 00: Negative Hysteresis Disabled. 01: Negative Hysteresis = 5 mV. 10: Negative Hysteresis = 10 mV. 11: Negative Hysteresis = 20 mV. C8051T600/1/2/3/4/5 CP0FIF CP0HYP[1:0] R/W R/W R/W 0 ...
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... C8051T600/1/2/3/4/5/6 SFR Definition 13.2. CPT0MD: Comparator0 Mode Selection Bit 7 6 Name R R Type 0 0 Reset SFR Address = 0x9D Bit Name 7:2 Unused Unused. Read = 000000b, Write = Don’t Care. 1:0 CP0MD[1:0] Comparator0 Mode Select. These bits affect the response time and power consumption for Comparator0. ...
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... Comparator Multiplexer C8051T600/1/2/3/4/5/6 devices include an analog input multiplexer to connect Port I/O pins to the compar- ator inputs. The Comparator0 inputs are selected in the CPT0MX register (SFR Definition 13.3). The CMX0P1–CMX0P0 bits select the Comparator0 positive input; the CMX0N1–CMX0N0 bits select the Comparator0 negative input ...
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... C8051T600/1/2/3/4/5/6 SFR Definition 13.3. CPT0MX: Comparator0 MUX Selection Bit 7 6 Name R R Type 0 0 Reset SFR Address = 0x9F Bit Name 7:6 Unused Unused. Read = 00b; Write = Don’t Care. 5:4 CMX0N[1:0] Comparator0 Negative Input MUX Selection. 00: 01: 10: 11: 3:2 Unused Unused. Read = 00b; Write = Don’t Care. ...
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... ACCUMULATOR RESET CLOCK STOP IDLE Figure 14.1. CIP-51 Block Diagram C8051T600/1/2/3/4/5/6 Reset Input Power Management Modes On-chip Debug Logic ...
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... C8051T600/1/2/3/4/5/6 With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. The CIP-51 has a total of 109 instructions. The table below shows the total number of instructions that require each execu- tion time. Clocks to Execute 1 Number of Instructions 26 14.1. Instruction Set The instruction set of the CIP-51 System Controller is fully compatible with the standard MCS-51™ ...
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... direct byte ORL direct, #data OR immediate to direct byte XRL A, Rn Exclusive-OR Register to A XRL A, direct Exclusive-OR direct byte to A XRL A, @Ri Exclusive-OR indirect RAM to A XRL A, #data Exclusive-OR immediate to A XRL direct, A Exclusive- direct byte C8051T600/1/2/3/4/5/6 Bytes Rev. 1.2 Clock Cycles ...
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... C8051T600/1/2/3/4/5/6 Table 14.1. CIP-51 Instruction Set Summary (Continued) Mnemonic Description XRL direct, #data Exclusive-OR immediate to direct byte CLR A Clear A CPL A Complement Rotate A left RLC A Rotate A left through Carry RR A Rotate A right RRC A Rotate A right through Carry SWAP A Swap nibbles of A Data Transfer ...
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... Compare immediate to Register and jump if not equal CJNE @Ri, #data, rel Compare immediate to indirect and jump if not equal DJNZ Rn, rel Decrement Register and jump if not zero DJNZ direct, rel Decrement direct byte and jump if not zero NOP No operation C8051T600/1/2/3/4/5/6 Bytes Rev. 1.2 Clock Cycles ...
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... C8051T600/1/2/3/4/5/6 Notes on Registers, Operands and Addressing Modes Register R0–R7 of the currently selected register bank. @Ri - Data RAM location addressed indirectly through R0 or R1. rel - 8-bit, signed (twos complement) offset relative to the first byte of the following instruction. Used by SJMP and all conditional jumps. direct - 8-bit internal data location’s address. This could be a direct-access Data RAM location (0x00– ...
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... The DPL register is the low byte of the 16-bit DPTR. SFR Definition 14.2. DPH: Data Pointer High Byte Bit 7 6 Name Type 0 0 Reset SFR Address = 0x83 Bit Name 7:0 DPH[7:0] Data Pointer High. The DPH register is the high byte of the 16-bit DPTR. C8051T600/1/2/3/4/5 DPL[7:0] R Function DPH[7:0] R ...
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... C8051T600/1/2/3/4/5/6 SFR Definition 14.3. SP: Stack Pointer Bit 7 6 Name Type 0 0 Reset SFR Address = 0x81 Bit Name 7:0 SP[7:0] Stack Pointer. The Stack Pointer holds the location of the top of the stack. The stack pointer is incre- mented before every PUSH operation. The SP register defaults to 0x07 after reset. ...
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... The OV bit is cleared the ADD, ADDC, SUBB, MUL, and DIV instructions in all other cases User Flag 1. This is a bit-addressable, general purpose flag for use under software control. 0 PARITY Parity Flag. This bit is set to logic 1 if the sum of the eight bits in the accumulator is odd and cleared if the sum is even. C8051T600/1/2/3/4/5 RS[1:0] R/W R Function Rev ...
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... Program Memory The CIP-51 core has program memory space. The C8051T600/1 implements 8192 bytes of this program memory space as in-system, Byte-Programmable EPROM, organized in a contiguous block from addresses 0x0000 to 0x1FFF. Note that 512 bytes (0x1E00 – 0x1FFF) of this memory are reserved for fac- tory use and are not available for user program storage. The C8051T602/3 implements 4096 bytes of EPROM program memory space ...
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... Figure 15.2. RAM Memory Map 15.2.1. Internal RAM The 256 bytes of internal RAM on the C8051T600/1/2/3/4/5 are mapped into the data memory space from 0x00 through 0xFF. The 128 bytes of internal RAM on the C8051T606 are mapped into the data memory space from 0x00 through 0x7F. The 128 bytes of data memory from 0x00 to 0x7F on all devices are used for general purpose registers and scratch pad memory ...
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... C8051T600/1/2/3/4/5/6 15.2.1.1. General Purpose Registers The lower 32 bytes of data memory, locations 0x00 through 0x1F, may be addressed as four banks of gen- eral-purpose registers. Each bank consists of eight byte-wide registers designated R0 through R7. Only one of these banks may be enabled at a time. Two bits in the program status word, RS0 (PSW.3) and RS1 (PSW ...
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... SFRs used to configure and access the sub-systems unique to the C8051T600/1/2/3/4/5/6. This allows the addition of new functionality while retaining compatibility with the MCS-51™ instruction set. Table 16.1 lists the SFRs implemented in the C8051T600/1/2/3/4/5/6 device family. The SFR registers are accessed any time the direct addressing mode is used to access memory locations from 0x80 to 0xFF ...
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... C8051T600/1/2/3/4/5/6 Table 16.2. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved Register Address 0xC3 ADC0 Greater-Than Compare Low ADC0GTL 0xBE ADC0 High ADC0H 0xBD ADC0 Low ADC0L 0xC6 ADC0 Less-Than Compare Word High ADC0LTH ...
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... Temperature Sensor Offset Measurement Low TOFFL 0xE1 Port I/O Crossbar Control 0 XBR0 0xE2 Port I/O Crossbar Control 1 XBR1 0xE3 Port I/O Crossbar Control 2 XBR2 All other SFR Locations Reserved C8051T600/1/2/3/4/5/6 Description Rev. 1.2 Page 176 176 174 143 142 126 ...
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... C8051T600/1/2/3/4/5/6 17. Interrupts The C8051T600/1/2/3/4/5/6 includes an extended interrupt system supporting a total of 12 interrupt sources with two priority levels. The allocation of interrupt sources between on-chip peripherals and exter- nal input pins varies according to the specific version of the device. Each interrupt source has one or more associated interrupt-pending flag(s) located in an SFR ...
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... MCU Interrupt Sources and Vectors The C8051T600/1/2/3/4/5/6 MCUs support 12 interrupt sources. Software can simulate an interrupt by set- ting an interrupt-pending flag to logic 1. If interrupts are enabled for the flag, an interrupt request will be generated and the CPU will vector to the ISR address associated with the interrupt-pending flag. MCU interrupt sources, associated vector addresses, priority order and control bits are summarized in Table 17 ...
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... C8051T600/1/2/3/4/5/6 Table 17.1. Interrupt Summary Interrupt Source Interrupt Vector Reset 0x0000 External Interrupt 0 0x0003 (INT0) Timer 0 Overflow 0x000B External Interrupt 1 0x0013 (INT1) Timer 1 Overflow 0x001B UART0 0x0023 Timer 2 Overflow 0x002B SMB0 0x0033 ADC0 0x003B Window Compare ADC0 0x0043 Conversion Complete Programmable ...
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... This bit sets the masking of the Timer 0 interrupt. 0: Disable all Timer 0 interrupt. 1: Enable interrupt requests generated by the TF0 flag. 0 EX0 Enable External Interrupt 0. This bit sets the masking of External Interrupt 0. 0: Disable External Interrupt 0. 1: Enable interrupt requests generated by the INT0 input. C8051T600/1/2/3/4/5 ET2 ES0 ET1 R/W R/W ...
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... C8051T600/1/2/3/4/5/6 SFR Definition 17.2. IP: Interrupt Priority Bit 7 6 Name R R Type 1 1 Reset SFR Address = 0xB8; Bit-Addressable Bit Name 7:6 Unused Unused. Read = 11b, Write = Don't Care. 5 PT2 Timer 2 Interrupt Priority Control. This bit sets the priority of the Timer 2 interrupt. 0: Timer 2 interrupt set to low priority level. ...
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... Disable ADC0 Window Comparison interrupt. 1: Enable interrupt requests generated by ADC0 Window Compare flag (AD0WINT). 0 ESMB0 Enable SMBus (SMB0) Interrupt. This bit sets the masking of the SMB0 interrupt. 0: Disable all SMB0 interrupts. 1: Enable interrupt requests generated by SMB0. C8051T600/1/2/3/4/5 ECP0F EPCA0 EADC0 R/W ...
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... C8051T600/1/2/3/4/5/6 SFR Definition 17.4. EIP1: Extended Interrupt Priority 1 Bit 7 6 PCP0R Name R R Type 1 1 Reset SFR Address = 0xF6 Bit Name 7:6 Unused Unused. Read = 11b; Write = Don’t Care. 5 PCP0R Comparator0 (CP0) Rising Edge Interrupt Priority Control. This bit sets the priority of the CP0 rising edge interrupt. ...
Page 87
... IN1PL); the flag remains logic 0 while the input is inactive. The external interrupt source must hold the input active until the interrupt request is recognized. It must then deactivate the interrupt request before execution of the ISR completes or another interrupt request will be generated. C8051T600/1/2/3/4/5/6 IT1 IN1PL /INT1 Interrupt ...
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... C8051T600/1/2/3/4/5/6 SFR Definition 17.5. IT01CF: INT0/INT1 Configuration Bit 7 6 IN1PL IN1SL[2:0] Name R/W Type 0 0 Reset SFR Address = 0xE4 Bit Name 7 IN1PL INT1 Polarity. 0: INT1 input is active low. 1: INT1 input is active high. 6:4 IN1SL[2:0] INT1 Port Pin Selection Bits. These bits select which Port pin is assigned to INT1. Note that this pin assignment is independent of the Crossbar ...
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... Stop mode consumes the least power because the majority of the device is shut down with no clocks active. SFR Definition 18.1 describes the Power Control Register (PCON) used to control the C8051T600/1/2/3/4/5/6's stop and idle power man- agement modes. ...
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... C8051T600/1/2/3/4/5/6 18.2. Stop Mode Setting the Stop Mode Select bit (PCON.1) causes the controller core to enter stop mode as soon as the instruction that sets the bit completes execution. In stop mode the internal oscillator, CPU, and all digital peripherals are stopped; the state of the external oscillator circuit is not affected. Each analog peripheral (including the external oscillator circuit) may be shut down individually prior to entering stop mode ...
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... IDLE Idle Mode Select. Setting this bit will place the CIP-51 in Idle mode. This bit will always be read CPU goes into Idle mode. (Shuts off clock to CPU, but clock to Timers, Interrupts, Serial Ports, and Analog Peripherals are still active.) C8051T600/1/2/3/4/5 GF[5:0] ...
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... C8051T600/1/2/3/4/5/6 19. Reset Sources Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this reset state, the following occur: CIP-51 halts program execution Special Function Registers (SFRs) are initialized to their defined reset values External Port pins are forced to a known state ...
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... The V is disabled following a power-on reset. V RST RST Logic HIGH Logic LOW Power-On Reset Figure 19.2. Power-On and V C8051T600/1/2/3/4/5/6 ramps from ramp time is 1 ms; slower ramp times may DD reaches the V level. For ramp times less than DD RST ) is typically less than 0.3 ms. ...
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... C8051T600/1/2/3/4/5/6 19.2. Power-Fail Reset/V DD When a power-down transition or power irregularity causes V monitor will drive the RST pin low and hold the CIP- reset state (see Figure 19.2). When level above V , the CIP-51 will be released from the reset state. Note that even though internal data ...
Page 95
... The MEMERR bit (RSTSRC.6) is set following an EPROM error reset. The state of the RST pin is unaf- fected by this reset. 19.8. Software Reset Software may force a reset by writing the SWRSF bit (RSTSRC.4). The SWRSF bit will read 1 fol- lowing a software forced reset. The state of the RST pin is unaffected by this reset. C8051T600/1/2/3/4/5/6 Rev. 1.2 95 ...
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... C8051T600/1/2/3/4/5/6 SFR Definition 19.1. RSTSRC: Reset Source Bit 7 6 MEMERR C0RSEF Name R R Type 0 Varies Reset SFR Address = 0xEF Bit Name Description 7 Unused Unused. 6 MEMERR EPROM Error Reset Flag. 5 C0RSEF Comparator0 Reset Enable and Flag. 4 SWRSF Software Reset Force and Flag. ...
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... Refer to the “C2 Interface Specification” available at http://www.silabs.com for details on com- municating via the C2 interface. Section “27. C2 Interface” on page 178 has information about C2 register addresses for the C8051T600/1/2/3/4/5/6. 20.1.1. EPROM Write Procedure 1. Reset the device using the RST pin. ...
Page 98
... Reset the device: Write 0x02 and then 0x00 to the DEVCTL register. 20.2. Security Options The C8051T600/1/2/3/4/5/6 devices provide security options to prevent unauthorized viewing of proprie- tary program code and constants. A security byte in EPROM address space can be used to lock the pro- gram memory from being read or written across the C2 interface. When read, the RDLOCK and WRLOCK bits in register EPSTAT will indicate the lock status of the location currently addressed by EPADDR. Table 20.1 shows the security byte decoding. See Section “ ...
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... The EPBusy bit in register C2ADD will be set during the CRC operation, and cleared once the operation is complete. The 16-bit results will be available in the CRC1-0 registers. CRC1 is the MSB, and CRC0 is the LSB. The polynomial for the 16-bit CRC calculation is 0x1021 C8051T600/1/2/3/4/5/6 Rev. 1.2 99 ...
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... C8051T600/1/2/3/4/5/6 21. Oscillators and Clock Selection C8051T600/1/2/3/4/5/6 devices include a programmable internal high-frequency oscillator and an external oscillator drive circuit. The internal high-frequency oscillator can be enabled/disabled and calibrated using the OSCICN and OSCICL registers, as shown in Figure 21.1. The system clock can be sourced by the external oscillator circuit or the internal oscillator (default). The internal oscillator offers a selectable post- scaling feature, which is initially set to divide the clock by 8 ...
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... The internal oscillator period can be adjusted via the OSCICL register as defined by SFR Definition 21.1. On C8051T600/1/2/3/4/5/6 devices, OSCICL is factory calibrated to obtain a 24.5 MHz base frequency. The system clock may be derived from the programmed internal oscillator divided defined by the IFCN bits in register OSCICN ...
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... C8051T600/1/2/3/4/5/6 SFR Definition 21.2. OSCICN: Internal H-F Oscillator Control Bit 7 6 Name R R Type 0 0 Reset SFR Address = 0xB2 Bit Name 7:5 Unused Unused. Read = 000b; Write = Don’t Care 4 IFRDY Internal H-F Oscillator Frequency Ready Flag. 0: Internal H-F Oscillator is not running at programmed frequency. ...
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... Additionally, when using the external oscillator circuit in capacitor or RC mode, the associated Port pin should be configured as an analog input. In CMOS clock mode, the associated pin should be configured as a digital input. See Section “22.4. Port I/O Initialization” on page 114 for details on Port input mode selection. C8051T600/1/2/3/4/5/6 Rev. 1.2 103 ...
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... C8051T600/1/2/3/4/5/6 SFR Definition 21.3. OSCXCN: External Oscillator Control Bit 7 6 XOSCMD[2:0] Name R Type 0 0 Reset SFR Address = 0xB1 Bit Name 7 Unused Read = 0b; Write = Don’t Care 6:4 XOSCMD[2:0] External Oscillator Mode Select. 00x: External Oscillator circuit off. 010: External CMOS Clock Mode. ...
Page 105
... Since the frequency of roughly 150 kHz is desired, select the K Factor from the table in SFR Definition 21.3 (OSCXCN 22: 0.150 MHz = 3.0) 3 0.150 MHz 146 48.8 pF Therefore, the XFCN value to use in this example is 011b and pF. C8051T600/1/2/3/4/5/6 3 ...
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... C8051T600/1/2/3/4/5/6 22. Port Input/Output Digital and analog resources are available through eight I/O pins on the C8051T600/1/2/3/4/5, or six I/O pins on the C8051T606. Port pins P0.0-P0.7 can be defined as general-purpose I/O (GPIO), assigned to one of the internal digital resources, or assigned to an analog function as shown in Figure 22.1. Port pin P0 ...
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... Logic Value (Port Latch or Crossbar) PxMDIN.x (1 for digital) (0 for analog) To/From Analog Peripheral Px.x – Input Logic Value (Reads 0 when pin is configured as an analog I/O) Figure 22.2. Port I/O Cell Block Diagram C8051T600/1/2/3/4/5/6 VDD VDD (WEAK) GND Rev. 1.2 PORT PAD 107 ...
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... C8051T600/1/2/3/4/5/6 22.1.3. Interfacing Port I Logic All Port I/O configured for digital, open-drain operation are capable of interfacing to digital logic operating at a supply voltage higher than VDD and less than 5. external pullup resistor to the higher supply voltage is typically required for most systems. Important Note multi-voltage interface, the external pullup resistor should be sized to allow a current of at least 150 µ ...
Page 109
... This includes P0.0 - P0.7 pins which (CEX0-2 and ECI T1. have their XBR0 bit set to 0. Note: The crossbar will always assign UART0 pins to P0.4 and P0.5. Any pin used for GPIO C8051T600/1/2/3/4/5/6 Potentially Assignable Port Pins P0.0–P0.7 P0.0–P0.7 P0.0 P0 ...
Page 110
... C8051T600/1/2/3/4/5/6 22.2.3. Assigning Port I/O Pins to External Digital Event Capture Functions External digital event capture functions can be used to trigger an interrupt or wake the device from a low power mode when a transition occurs on a digital I/O pin. The digital event capture functions do not require dedicated pins and will function on both GPIO pins (XBR0 = 1) and pins in use by the crossbar (XBR0 = 0) ...
Page 111
... Pin Skip Settings XBR0 Figure 22.3. Priority Crossbar Decoder Potential Pin Assignments C8051T600/1/2/3/4/5/6 All Port 0 pins are capable of being assigned to crossbar peripherals. The crossbar peripherals are assigned in priority order from top to bottom, according to this diagram. These boxes represent Port 0 pins which can potentially be assigned to a peripheral ...
Page 112
... C8051T600/1/2/3/4/5/6 Port P0 Pin Special Function Signals TX0 RX0 SDA SCL CP0 CP0A SYSCLK CEX0 CEX1 CEX2 ECI Pin Skip Settings XBR0 Figure 22.4. Priority Crossbar Decoder Example Skipped Pins 112 In this example, the crossbar is configured to assign the UART TX0 and RX0 signals, the SMBus signals, and the SYSCLK signal ...
Page 113
... SCL). UART0 pin assignments are fixed for bootloading purposes: UART TX0 is always assigned to P0.4; UART RX0 is always assigned to P0.5. Standard Port I/Os appear contiguously after the prioritized func- tions have been assigned. C8051T600/1/2/3/4/5/6 In this example, the crossbar is configured to assign the UART TX0 and RX0 signals, the SMBus signals, and the SYSCLK signal ...
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... C8051T600/1/2/3/4/5/6 22.4. Port I/O Initialization Port I/O initialization consists of the following steps: 1. Select the input mode (analog or digital) for all Port pins, using the Port Input Mode register (P0MDIN). 2. Select the output mode (open-drain or push-pull) for all Port pins, using the Port Output Mode register (P0MDOUT) ...
Page 115
... These bits select port pins to be skipped by the crossbar decoder. Port pins used for analog, special functions or GPIO should be skipped by the crossbar. 0: Corresponding P0.n pin is not skipped by the crossbar. 1: Corresponding P0.n pin is skipped by the crossbar. Note: Bits 6 and 0 on the C8051T606 are read-only with a reset value of ‘1’. C8051T600/1/2/3/4/5 XSKP[6:0] ...
Page 116
... C8051T600/1/2/3/4/5/6 SFR Definition 22.2. XBR1: Port I/O Crossbar Register 1 Bit 7 6 PCA0ME[1:0] Name R/W R/W Type 0 0 Reset SFR Address = 0xE2 Bit Name 7:6 PCA0ME[1:0] PCA Module I/O Enable Bits. 00: All PCA I/O unavailable at Port pins. 01: CEX0 routed to Port pin. 10: CEX0, CEX1 routed to Port pins. ...
Page 117
... Unused. Read = 000b; Write = Don’t Care. 2 T1E T1 Enable unavailable at Port pin routed to Port pin. 1 T0E T0 Enable unavailable at Port pin routed to Port pin. 0 ECIE PCA0 External Counter Input Enable. 0: ECI unavailable at Port pin. 1: ECI routed to Port pin. C8051T600/1/2/3/4/5 T1E R Function Rev. 1 ...
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... C8051T600/1/2/3/4/5/6 22.5. Special Function Registers for Accessing and Configuring Port I/O The Port I/O pins are accessed through the special function register P0, which is both byte addressable and bit addressable. When writing to this SFR, the value written is latched to maintain the output data value at each pin ...
Page 119
... Bit Name 7:0 P0MDOUT[7:0] Output Configuration Bits for P0.7–P0.0 (respectively). These bits are ignored if the corresponding bit in register P0MDIN is logic 0. 0: Corresponding P0.n Output is open-drain. 1: Corresponding P0.n Output is push-pull. Note: Bits 6 and 0 on the C8051T606 are read-only. C8051T600/1/2/3/4/5 P0MDIN[7:0] R/W 1 ...
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... C8051T600/1/2/3/4/5/6 23. SMBus The SMBus I/O interface is a two-wire, bi-directional serial bus. The SMBus is compliant with the System Management Bus Specification, version 1.1, and compatible with the I the interface by the system controller are byte oriented with the SMBus interface autonomously controlling the serial transfer of the data. Data can be transferred 1/20th of the system clock as a master or slave (this can be faster than allowed by the SMBus specification, depending on the system clock used) ...
Page 121
... Figure 23.3). If the receiving device does not ACK, the transmitting device will read a NACK (not acknowl- edge), which is a high SDA during a high SCL. The direction bit (R/W) occupies the least-significant bit position of the address byte. The direction bit is set to logic 1 to indicate a "READ" operation and cleared to logic 0 to indicate a "WRITE" operation. C8051T600/1/2/3/4/5/6 VDD = 5V VDD = 3V Slave ...
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... C8051T600/1/2/3/4/5/6 All transactions are initiated by a master, with one or more addressed slave devices as the target. The master generates the START condition and then transmits the slave address and direction bit. If the trans- action is a WRITE operation from the master to the slave, the master transmits the data a byte at a time and waits for an ACK from the slave at the end of each byte ...
Page 123
... NACK all received addresses and will not generate any slave interrupts. When the INH bit is set, all slave events will be inhibited following the next START (interrupts will continue for the duration of the current transfer). C8051T600/1/2/3/4/5/6 Rev. 1.2 123 ...
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... C8051T600/1/2/3/4/5/6 Table 23.1. SMBus Clock Source Selection SMBCS1 The SMBCS1–0 bits select the SMBus clock source, which is used only when operating as a master or when the Free Timeout detection is enabled. When operating as a master, overflows from the selected source determine the absolute minimum SCL low and high times as defined in Equation 23.1. Note that the selected clock source may be shared by other peripherals so long as the timer is left running at all times ...
Page 125
... SMBus Free Timeout detection can be enabled by setting the SMBFTE bit. When this bit is set, the bus will be considered free if SDA and SCL remain high for more than 10 SMBus clock source periods (see Figure 23.4). C8051T600/1/2/3/4/5/6 Minimum SDA Hold Time – 4 system clocks ...
Page 126
... C8051T600/1/2/3/4/5/6 SFR Definition 23.1. SMB0CF: SMBus Clock/Configuration Bit 7 6 ENSMB INH Name R/W R/W Type 0 0 Reset SFR Address = 0xC1 Bit Name 7 ENSMB SMBus Enable. This bit enables the SMBus interface when set to 1. When enabled, the interface constantly monitors the SDA and SCL pins. ...
Page 127
... Important Note About the SI Bit: The SMBus interface is stalled while SI is set; thus SCL is held low, and the bus is stalled until software clears SI. Table 23.3 lists all sources for hardware changes to the SMB0CN bits. Refer to Table 23.4 for SMBus sta- tus decoding using the SMB0CN register. C8051T600/1/2/3/4/5/6 Rev. 1.2 127 ...
Page 128
... C8051T600/1/2/3/4/5/6 SFR Definition 23.2. SMB0CN: SMBus Control Bit 7 6 MASTER TXMODE Name R R Type 0 0 Reset SFR Address = 0xC0; Bit-Addressable Bit Name Description 7 MASTER SMBus Master/Slave Indicator. This read-only bit indicates when the SMBus is operating as a master. 6 TXMODE SMBus Transmit Mode Indicator ...
Page 129
... A byte has been transmitted and an ACK/NACK received. SI A byte has been received. A START or repeated START followed by a slave address + R/W has been received. A STOP has been received. C8051T600/1/2/3/4/5/6 Cleared by Hardware When: A STOP is generated. Arbitration is lost. A START is detected. Arbitration is lost. ...
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... C8051T600/1/2/3/4/5/6 23.4.3. Data Register The SMBus Data register SMB0DAT holds a byte of serial data to be transmitted or one that has just been received. Software may safely read or write to the data register when the SI flag is set. Software should not attempt to access the SMB0DAT register when the SMBus is enabled and the SI flag is cleared to logic 0, as the interface may be in the process of shifting a byte of data into or out of the register ...
Page 131
... Notice that all of the “data byte transferred” interrupts occur after the ACK cycle in this mode. S SLA W Received by SMBus Interface Transmitted by SMBus Interface Figure 23.5. Typical Master Write Sequence C8051T600/1/2/3/4/5/6 A Data Byte A Data Byte Interrupt Locations S = START P = STOP A = ACK W = WRITE SLA = Slave Address Rev ...
Page 132
... C8051T600/1/2/3/4/5/6 23.5.2. Read Sequence (Master) During a read sequence, an SMBus master reads data from a slave device. The master in this transfer will be a transmitter during the address byte, and a receiver during all data bytes. The SMBus interface gener- ates the START condition and transmits the first byte containing the address of the target slave and the data direction bit ...
Page 133
... Two received data bytes are shown, though any number of bytes may be received. Notice that the ‘data byte transferred’ interrupts occur before the ACK. S SLA W Received by SMBus Interface Transmitted by SMBus Interface Figure 23.7. Typical Slave Write Sequence C8051T600/1/2/3/4/5/6 A Data Byte A Data Byte Interrupt Locations S = START P = STOP A = ACK W = WRITE SLA = Slave Address Rev ...
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... C8051T600/1/2/3/4/5/6 23.5.4. Read Sequence (Slave) During a read sequence, an SMBus master reads data from a slave device. The slave in this transfer will be a receiver during the address byte, and a transmitter during all data bytes. When slave events are enabled (INH = 0), the interface enters Slave Receiver Mode (to receive the slave address) when a START followed by a slave address and direction bit (READ in this case) is received ...
Page 135
... ACK received. A master data byte was 1000 received; ACK requested. C8051T600/1/2/3/4/5/6 Typical Response Options Load slave address + R/W into SMB0DAT. Set STA to restart transfer. Abort transfer. Load next data byte into SMB0DAT. End transfer with STOP. End transfer with STOP and start another transfer ...
Page 136
... C8051T600/1/2/3/4/5/6 Table 23.4. SMBus Status Decoding Values Read Current SMbus State A slave byte was transmitted NACK received. A slave byte was transmitted; 0100 ACK received. A slave byte was transmitted error detected. An illegal STOP or bus error 0101 was detected while a Slave Transmission was in progress. ...
Page 137
... CPU vectors to the interrupt service routine. They must be cleared manually by software, allowing software to determine the cause of the UART0 interrupt (transmit complete or receive complete). Write to SBUF UART Baud Rate Generator Figure 24.1. UART0 Block Diagram C8051T600/1/2/3/4/5/6 SFR Bus TB8 SBUF SET (TX Shift ...
Page 138
... C8051T600/1/2/3/4/5/6 24.1. Enhanced Baud Rate Generation The UART0 baud rate is generated by Timer 1 in 8-bit auto-reload mode. The TX clock is generated by TL1; the RX clock is generated by a copy of TL1 (shown as RX Timer in Figure 24.2), which is not user- accessible. Both TX and RX Timer overflows are divided by two to generate the TX and RX baud rates. ...
Page 139
... RI0 flag is set. If these conditions are not met, SBUF0 and RB80 will not be loaded and the RI0 flag will not be set. An interrupt will occur if enabled when either TI0 or RI0 is set. MARK START D0 D1 BIT SPACE BIT TIMES BIT SAMPLING Figure 24.4. 8-Bit UART Timing Diagram C8051T600/1/2/3/4/5/6 TX RS-232 RS-232 C8051xxxx LEVEL RX XLTR ...
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... C8051T600/1/2/3/4/5/6 24.2.2. 9-Bit UART The 9-bit UART mode uses a total of eleven bits per data byte: a start bit, 8 data bits (LSB first), a program- mable ninth data bit, and a stop bit. The state of the ninth transmit data bit is determined by the value in TB80 (SCON0.3), which is assigned by user software. It can be assigned the value of the parity flag (bit P in register PSW) for error detection, or used in multiprocessor communications ...
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... Master Slave Device Device Figure 24.6. UART Multi-Processor Mode Interconnect Diagram C8051T600/1/2/3/4/5/6 Slave Slave Device Device Rev. 1.2 V+ ...
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... C8051T600/1/2/3/4/5/6 SFR Definition 24.1. SCON0: Serial Port 0 Control Bit 7 6 Name S0MODE R/W R Type 0 1 Reset SFR Address = 0x98; Bit-Addressable Bit Name 7 S0MODE Serial Port 0 Operation Mode. Selects the UART0 Operation Mode. 0: 8-bit UART with Variable Baud Rate. 1: 9-bit UART with Variable Baud Rate. ...
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... This SFR accesses two registers; a transmit shift register and a receive latch register. When data is written to SBUF0, it goes to the transmit shift register and is held for serial transmission. Writing a byte to SBUF0 initiates the transmission. A read of SBUF0 returns the contents of the receive latch. C8051T600/1/2/3/4/5 ...
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... C8051T600/1/2/3/4/5/6 Table 24.1. Timer Settings for Standard Baud Rates Using The Internal 24.5 MHz Oscillator Target Baud Rate % Error Baud Rate (bps) 230400 –0.32% 115200 –0.32% 57600 0.15% 28800 –0.32% 14400 0.15% 9600 –0.32% 2400 –0.32% 1200 0.15% Notes: – 1. SCA1 SCA0 and T1M bit definitions can be found Don’ ...
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... The input signal need not be peri- odic, but it should be held at a given level for at least two full system clock cycles to ensure the level is properly sampled. C8051T600/1/2/3/4/5/6 Timer 2 Modes: 16-bit timer with auto-reload Two 8-bit timers with auto-reload Rev ...
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... C8051T600/1/2/3/4/5/6 SFR Definition 25.1. CKCON: Clock Control Bit 7 6 T2MH Name R R/W Type 0 0 Reset SFR Address = 0x8E Bit Name 7 Unused Unused. Read = 0b, Write = Don’t Care 6 T2MH Timer 2 High Byte Clock Select. Selects the clock supplied to the Timer 2 high byte (split 8-bit timer mode only). ...
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... TL1 and TH1 form the 13-bit register for Timer 1 in the same manner as described above for TL0 and TH0. Timer 1 is configured and controlled using the relevant TCON and TMOD bits just as with Timer 0. The input signal INT0 is used with Timer 1; the /INT1 polarity is defined by bit IN1PL in register IT01CF (see SFR Definition 17.5). C8051T600/1/2/3/4/5/6 GATE0 INT0 Counter/Timer ...
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... C8051T600/1/2/3/4/5/6 Pre-scaled Clock SYSCLK T0 GATE0 Crossbar IN0PL XOR INT0 Figure 25.1. T0 Mode 0 Block Diagram 25.1.2. Mode 1: 16-bit Counter/Timer Mode 1 operation is the same as Mode 0, except that the counter/timer registers use all 16 bits. The coun- ter/timers are enabled and configured in Mode 1 in the same manner as for Mode 0. ...
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... INT0 is active as defined by bit IN0PL in register IT01CF (see Section “17.3. INT0 and INT1 External Interrupt Sources” on page 87 for details on the external input signals INT0 and INT1). T0M Pre-scaled Clock SYSCLK T0 Crossbar GATE0 IN0PL XOR INT0 Figure 25.2. T0 Mode 2 Block Diagram C8051T600/1/2/3/4/5/6 TMOD IT01CF ...
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... C8051T600/1/2/3/4/5/6 25.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only) In Mode 3, Timer 0 is configured as two separate 8-bit counter/timers held in TL0 and TH0. The coun- ter/timer in TL0 is controlled using the Timer 0 control/status bits in TCON and TMOD: TR0, C/T0, GATE0, and TF0. TL0 can use either the system clock or an external input signal as its timebase. The TH0 register is restricted to a timer function sourced by the system clock or prescaled clock ...
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... IT0 Interrupt 0 Type Select. This bit selects whether the configured INT0 interrupt will be edge or level sensitive. INT0 is configured active low or high by the IN0PL bit in register IT01CF (see SFR Definition 17.5). 0: INT0 is level triggered. 1: INT0 is edge triggered. C8051T600/1/2/3/4/5 TF0 TR0 IE1 R/W ...
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... C8051T600/1/2/3/4/5/6 SFR Definition 25.3. TMOD: Timer Mode Bit 7 6 GATE1 C/T1 Name R/W R/W Type 0 0 Reset SFR Address = 0x89 Bit Name 7 GATE1 Timer 1 Gate Control. 0: Timer 1 enabled when TR1 = 1 irrespective of INT1 logic level. 1: Timer 1 enabled only when TR1 = 1 AND INT1 is active as defined by bit IN1PL in register IT01CF (see SFR Definition 17 ...
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... The TL0 register is the low byte of the 16-bit Timer 0. SFR Definition 25.5. TL1: Timer 1 Low Byte Bit 7 6 Name Type 0 0 Reset SFR Address = 0x8B Bit Name 7:0 TL1[7:0] Timer 1 Low Byte. The TL1 register is the low byte of the 16-bit Timer 1. C8051T600/1/2/3/4/5 TL0[7:0] R Function TL1[7:0] R ...
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... C8051T600/1/2/3/4/5/6 SFR Definition 25.6. TH0: Timer 0 High Byte Bit 7 6 Name Type 0 0 Reset SFR Address = 0x8C Bit Name 7:0 TH0[7:0] Timer 0 High Byte. The TH0 register is the high byte of the 16-bit Timer 0. SFR Definition 25.7. TH1: Timer 1 High Byte Bit ...
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... T2XCLK T2ML SYSCLK / External Clock / 8 1 SYSCLK 1 Figure 25.4. Timer 2 16-Bit Mode Block Diagram C8051T600/1/2/3/4/5/6 To SMBus TL2 Overflow TCLK TR2 TMR2L TMR2H TMR2RLL TMR2RLH Reload Rev. 1.2 To ADC, ...
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... C8051T600/1/2/3/4/5/6 25.2.2. 8-bit Timers with Auto-Reload When T2SPLIT is set, Timer 2 operates as two 8-bit timers (TMR2H and TMR2L). Both 8-bit timers oper- ate in auto-reload mode as shown in Figure 25.5. TMR2RLL holds the reload value for TMR2L; TMR2RLH holds the reload value for TMR2H. The TR2 bit in TMR2CN handles the run control for TMR2H. TMR2L is always running when configured for 8-bit Mode ...
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... Timer 2 Clock Select bits (T2MH and T2ML in register CKCON) may still be used to select between the external clock and the system clock for either timer. 0: Timer 2 clock is the system clock divided by 12. 1: Timer 2 clock is the external clock divided by 8 (synchronized with SYSCLK). C8051T600/1/2/3/4/5 ...
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... C8051T600/1/2/3/4/5/6 SFR Definition 25.9. TMR2RLL: Timer 2 Reload Register Low Byte Bit 7 6 Name Type 0 0 Reset SFR Address = 0xCA Bit Name 7:0 TMR2RLL[7:0] Timer 2 Reload Register Low Byte. TMR2RLL holds the low byte of the reload value for Timer 2. SFR Definition 25.10. TMR2RLH: Timer 2 Reload Register High Byte ...
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... Name Type 0 0 Reset SFR Address = 0xCD Bit Name 7:0 TMR2H[7:0] Timer 2 Low Byte. In 16-bit mode, the TMR2H register contains the high byte of the 16-bit Timer bit mode, TMR2H contains the 8-bit high byte timer value. C8051T600/1/2/3/4/5 TMR2H[7:0] R Function Rev. 1.2 ...
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... C8051T600/1/2/3/4/5/6 26. Programmable Counter Array The Programmable Counter Array (PCA0) provides enhanced timer functionality while requiring less CPU intervention than the standard 8051 counter/timers. The PCA consists of a dedicated 16-bit counter/timer and three 16-bit Capture/Compare modules. Each Capture/Compare module has its own associated I/O line (CEXn) which is routed through the Crossbar to Port I/O when enabled ...
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... ECI 011 SYSCLK 100 External Clock/8 101 Figure 26.2. PCA Counter/Timer Block Diagram C8051T600/1/2/3/4/5/6 Timebase System clock divided by 12 System clock divided by 4 Timer 0 overflow High-to-low transitions on ECI (max rate = system clock divided by 4) System clock External oscillator source divided by 8 ...
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... C8051T600/1/2/3/4/5/6 26.2. PCA0 Interrupt Sources Figure 26.3 shows a diagram of the PCA interrupt tree. There are four independent event flags that can be used to generate a PCA0 interrupt. They are: the main PCA counter overflow flag (CF), which is set upon a 16-bit overflow of the PCA0 counter, and the individual flags for each PCA channel (CCF0, CCF1, and CCF2), which are set according to the operation mode of that module ...
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... B = When set to 0, the digital comparator is off. For high speed and frequency output modes, the associated pin will not toggle. In any of the PWM modes, this generates a 0% duty cycle (output = 0 When set, a match event will cause the CCFn flag for the associated channel to be set. C8051T600/1/2/3/4/5/6 Bit Number ...
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... C8051T600/1/2/3/4/5/6 26.3.1. Edge-triggered Capture Mode In this mode, a valid transition on the CEXn pin causes the PCA to capture the value of the PCA coun- ter/timer and load it into the corresponding module's 16-bit Capture/Compare register (PCA0CPLn and PCA0CPHn). The CAPPn and CAPNn bits in the PCA0CPMn register are used to select the type of transi- tion that triggers the capture: low-to-high transition (positive edge), high-to-low transition (negative edge), or either transition (positive or negative edge) ...
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... Writing to PCA0CPLn clears the ECOMn bit to 0; writing to PCA0CPHn sets ECOMn to 1. Write to PCA0CPLn 0 ENB Reset Write to PCA0CPHn ENB 1 PCA0CPMn Enable Figure 26.5. PCA Software Timer Mode Diagram C8051T600/1/2/3/4/5/6 PCA0CPLn PCA0CPHn Match 16-bit Comparator PCA PCA0L PCA0H Timebase Rev. 1.2 PCA Interrupt PCA0CN 165 ...
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... C8051T600/1/2/3/4/5/6 26.3.3. High-Speed Output Mode In High-Speed Output mode, a module’s associated CEXn pin is toggled each time a match occurs between the PCA Counter and the module's 16-bit Capture/Compare register (PCA0CPHn and PCA0CPLn). When a match occurs, the Capture/Compare Flag (CCFn) in PCA0CN is set to logic 1. An interrupt request is generated if the CCFn interrupt for that module is enabled ...
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... ENB Reset PCA0CPMn Write PCA0CPHn ENB Figure 26.7. PCA Frequency Output Mode C8051T600/1/2/3/4/5/6 F PCA ---------------------------------------- - F = CEXn 2 PCA0CPHn E C PCA0CPLn 8-bit Adder C F Adder n Enable Toggle x 8-bit match Enable Comparator PCA Timebase PCA0L Rev. 1.2 PCA0CPHn TOGn 0 CEXn Crossbar Port I/O 1 167 ...
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... C8051T600/1/2/3/4/5/6 26.3.5. 8-bit Pulse Width Modulator Mode The duty cycle of the PWM output signal in 8-bit PWM mode is varied using the module's PCA0CPLn Cap- ture/Compare register. When the value in the low byte of the PCA counter/timer (PCA0L) is equal to the value in PCA0CPLn, the output on the CEXn pin will be set. When the count value in PCA0L overflows, the CEXn output will be reset (see Figure 26.8). Also, when the counter/timer low byte (PCA0L) overflows from 0xFF to 0x00, PCA0CPLn is reloaded automatically with the value stored in the module’ ...
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... PCA0CPLn 0 ENB Reset Write to PCA0CPHn ENB 1 PCA0CPMn PCA Timebase Figure 26.9. PCA 16-Bit PWM Mode C8051T600/1/2/3/4/5/6 65536 PCA0CPn – ---------------------------------------------------- - = 65536 PCA0CPHn PCA0CPLn match Enable 16-bit Comparator S R PCA0H PCA0L Overflow Rev. 1.2 CEXn SET Q Crossbar Port I/O Q CLR 169 ...
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... C8051T600/1/2/3/4/5/6 26.4. Watchdog Timer Mode A programmable Watchdog Timer (WDT) function is available through the PCA Module 2. The WDT is used to generate a reset if the time between writes to the WDT update register (PCA0CPH2) exceed a specified limit. The WDT can be configured and enabled/disabled as needed by software. With the WDTE bit set in the PCA0MD register, Module 2 operates as a Watchdog Timer (WDT). The Mod- ule 2 high byte is compared to the PCA counter high byte ...
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... The WDT is enabled following any reset. The PCA0 counter clock defaults to the system clock divided by 12, PCA0L defaults to 0x00, and PCA0CPL2 defaults to 0x00. Using Equation 26.4, this results in a WDT timeout interval of 256 PCA clock cycles, or 3072 system clock cycles. Table 26.3 lists some example tim- eout intervals for typical system clocks. C8051T600/1/2/3/4/5/6 ...
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... C8051T600/1/2/3/4/5/6 Table 26.3. Watchdog Timer Timeout Intervals System Clock (Hz) 24,500,000 24,500,000 24,500,000 3,062,500 3,062,500 3,062,500 32,000 32,000 32,000 Notes: 1. Assumes SYSCLK/12 as the PCA clock source and a PCA0L value of 0x00 at the update time. 2. Internal SYSCLK reset frequency = Internal Oscillator divided by 8. 172 ...
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... PCA Module 0 Capture/Compare Flag. This bit is set by hardware when a match or capture occurs. When the CCF0 interrupt is enabled, setting this bit causes the CPU to vector to the PCA interrupt service rou- tine. This bit is not automatically cleared by hardware and must be cleared by software. C8051T600/1/2/3/4/5 ...
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... C8051T600/1/2/3/4/5/6 SFR Definition 26.2. PCA0MD: PCA Mode Bit 7 6 CIDL WDTE WDLCK Name R/W R/W Type 0 1 Reset SFR Address = 0xD9 Bit Name 7 CIDL PCA Counter/Timer Idle Control. Specifies PCA behavior when CPU is in Idle Mode. 0: PCA continues to function normally while the system controller is in Idle Mode. ...
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... Enable a Capture/Compare Flag interrupt request when CCFn is set. Note: When the WDTE bit is set to 1, the PCA0CPM2 register cannot be modified, and module 2 acts as the Watchdog Timer. To change the contents of the PCA0CPM2 register or the function of module 2, the Watchdog Timer must be disabled. C8051T600/1/2/3/4/5 ...
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... C8051T600/1/2/3/4/5/6 SFR Definition 26.4. PCA0L: PCA Counter/Timer Low Byte Bit 7 6 Name R/W R/W Type 0 0 Reset SFR Address = 0xF9 Bit Name 7:0 PCA0[7:0] PCA Counter/Timer Low Byte. The PCA0L register holds the low byte (LSB) of the 16-bit PCA Counter/Timer. Note: When the WDTE bit is set to 1, the PCA0L register cannot be modified by software. To change the contents of the PCA0L register, the Watchdog Timer must first be disabled ...
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... Reset SFR Addresses: PCA0CPH0 = 0xFC Bit Name 7:0 PCA0CPn[15:8] PCA Capture Module High Byte. The PCA0CPHn register holds the high byte (MSB) of the 16-bit capture module n. Note: A write to this register will set the module’s ECOMn bit C8051T600/1/2/3/4/5 PCA0CPn[7:0] R/W R/W ...
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... C8051T600/1/2/3/4/5/6 27. C2 Interface C8051T600/1/2/3/4/5/6 devices include an on-chip Silicon Labs 2-Wire (C2) debug interface to allow EPROM programming and in-system debugging with the production part installed in the end application. The C2 interface operates using only two pins: a bi-directional data signal (C2D), and a clock input (C2CK). See the C2 Interface Specification for details on the C2 protocol. ...
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... C2 Register Definition 27.2. DEVICEID: C2 Device ID Bit 7 6 Name Type 0 0 Reset C2 Address: 0x00 Bit Name 7:0 DEVICEID[7:0] Device ID. This read-only register returns the 8-bit device ID: 0x10 = C8051T600/1/2/3/4/5 0x1B = C8051T606 C2 Register Definition 27.3. REVID: C2 Revision ID Bit 7 6 Name Type Varies Varies Varies Reset C2 Address: 0x01 Bit ...
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... C8051T600/1/2/3/4/5/6 C2 Register Definition 27.4. DEVCTL: C2 Device Control Bit 7 6 Name Type 0 0 Reset C2 Address: 0x02 Bit Name 7:0 DEVCTL[7:0] Device Control Register. This register is used to halt the device for EPROM operations via the C2 interface. Refer to the EPROM chapter for more information. ...
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... Set EPADDR currently points to a write-locked address. 6 RDLOCK Read Lock Indicator. Set EPADDR currently points to a read-locked address. 5:1 Unused Unused. Read = Varies; Write = Don’t Care. 0 ERROR Error Indicator. Set last EPROM read or write operation failed due to a security restriction. C8051T600/1/2/3/4/5 EPDAT[7:0] R Function 5 4 ...
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... C8051T600/1/2/3/4/5/6 C2 Register Definition 27.8. EPADDRH: C2 EPROM Address High Byte Bit 7 6 Name Type 0 0 Reset C2 Address: 0xAF Bit Name 7:0 EPADDR[15:8] C2 EPROM Address High Byte. This register is used to set the EPROM address location during C2 EPROM oper- ations. C2 Register Definition 27.9. EPADDRL: C2 EPROM Address Low Byte ...
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... CRC[15:8] CRC Byte 1. A write to this register initiates a 32-bit CRC on the entire program memory space. The CRC begins at address 0x0000. When complete, the 32-bit result is stored in CRC3 (MSB), CRC2, CRC1, and CRC0 (LSB). See Section “20.3. Program Memory CRC” on page 99. C8051T600/1/2/3/4/5 CRC[7:0] ...
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... C8051T600/1/2/3/4/5/6 C2 Register Definition 27.12. CRC2: CRC Byte 2 Bit 7 6 Name Type 0 0 Reset C2 Address: 0xAB Bit Name 7:0 CRC[23:16] CRC Byte 2. See Section “20.3. Program Memory CRC” on page 99. C2 Register Definition 27.13. CRC3: CRC Byte 3 Bit 7 6 Name Type 0 0 Reset ...
Page 185
... The configuration in Figure 27.1 assumes the following: 1. The user input (b) cannot change state while the target device is halted. 2. The RST pin on the target device is used as an input only. Additional resistors may be necessary depending on the specific application. C8051T600/1/2/3/4/5/6 C2CK C2D C2 Interface Master Rev ...
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... C8051T600/1/2/3/4/5 OCUMENT HANGE IST Revision 0.5 to Revision 1.0 Updated electrical specification tables based on test, characterization, and qualification data. Updated with new formatting standards. Corrected minor typographical errors throughout document. Updated wording from “OTP EPROM” to “EPROM” throughout document. ...
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... N : OTES C8051T600/1/2/3/4/5/6 Rev. 1.2 187 ...
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... C8051T600/1/2/3/4/5 ONTACT NFORMATION Silicon Laboratories Inc. Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Please visit the Silicon Labs Technical Support and register to submit a technical support request. ...