C8051T600-GS Silicon Laboratories Inc, C8051T600-GS Datasheet - Page 85

• Manufacturer Part Number: C8051T600-GS
• Description: IC 8051 MCU 8K OTP 14SOIC
• Manufacturer: Silicon Laboratories Inc
• Series: C8051T60xr

Specifications of C8051T600-GS

• Program Memory Type: OTP
• Program Memory Size: 8KB (8K x 8)
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051T6x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C/SMBus/UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 8
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051T600DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Package: 14SOIC
• Device Core: 8051
• Family Name: C8051T60x
• Maximum Speed: 25 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1665 - BOARD DAUGHTER FOR C8051T600E336-1404 - KIT DEV FOR C8051T60X MCU'S
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1403-5

SFR Definition 17.3. EIE1: Extended Interrupt Enable 1
SFR Address = 0xE6
Name
Reset
Bit
7:6
Type
5
4
3
2
1
0
Bit
EWADC0 Enable Window Comparison ADC0 Interrupt.
Unused
ESMB0
ECP0R
EPCA0
EADC0
ECP0F
Name
R
7
0
Unused. Read = 00b; Write = Don’t Care.
Enable Comparator0 (CP0) Rising Edge Interrupt.
This bit sets the masking of the CP0 rising edge interrupt.
0: Disable CP0 rising edge interrupts.
1: Enable interrupt requests generated by the CP0RIF flag.
Enable Comparator0 (CP0) Falling Edge Interrupt.
This bit sets the masking of the CP0 falling edge interrupt.
0: Disable CP0 falling edge interrupts.
1: Enable interrupt requests generated by the CP0FIF flag.
Enable Programmable Counter Array (PCA0) Interrupt.
This bit sets the masking of the PCA0 interrupts.
0: Disable all PCA0 interrupts.
1: Enable interrupt requests generated by PCA0.
Enable ADC0 Conversion Complete Interrupt.
This bit sets the masking of the ADC0 Conversion Complete interrupt.
0: Disable ADC0 Conversion Complete interrupt.
1: Enable interrupt requests generated by the AD0INT flag.
This bit sets the masking of ADC0 Window Comparison interrupt.
0: Disable ADC0 Window Comparison interrupt.
1: Enable interrupt requests generated by ADC0 Window Compare flag (AD0WINT).
Enable SMBus (SMB0) Interrupt.
This bit sets the masking of the SMB0 interrupt.
0: Disable all SMB0 interrupts.
1: Enable interrupt requests generated by SMB0.
R
6
0
ECP0R
R/W
5
0
ECP0F
R/W
Rev. 1.2
4
0
Function
C8051T600/1/2/3/4/5/6
EPCA0
R/W
3
0
EADC0
R/W
2
0
EWADC0
R/W
1
0
ESMB0
R/W
0
0
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