C8051T600-GS Silicon Laboratories Inc, C8051T600-GS Datasheet - Page 142

• Manufacturer Part Number: C8051T600-GS
• Description: IC 8051 MCU 8K OTP 14SOIC
• Manufacturer: Silicon Laboratories Inc
• Series: C8051T60xr

Specifications of C8051T600-GS

• Program Memory Type: OTP
• Program Memory Size: 8KB (8K x 8)
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051T6x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C/SMBus/UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 8
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051T600DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Package: 14SOIC
• Device Core: 8051
• Family Name: C8051T60x
• Maximum Speed: 25 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1665 - BOARD DAUGHTER FOR C8051T600E336-1404 - KIT DEV FOR C8051T60X MCU'S
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1403-5

C8051T600/1/2/3/4/5/6
SFR Definition 24.1. SCON0: Serial Port 0 Control
SFR Address = 0x98; Bit-Addressable
142
Name S0MODE
Reset
Bit
Type
7
6
5
4
3
2
1
0
Bit
S0MODE Serial Port 0 Operation Mode.
Unused
Name
MCE0
REN0
RB80
TB80
RI0
TI0
R/W
7
0
Selects the UART0 Operation Mode.
0: 8-bit UART with Variable Baud Rate.
1: 9-bit UART with Variable Baud Rate.
Unused. Read = 1b, Write = Don’t Care.
Multiprocessor Communication Enable.
The function of this bit is dependent on the Serial Port 0 Operation Mode:
Mode 0: Checks for valid stop bit.
0: Logic level of stop bit is ignored.
1: RI0 will only be activated if stop bit is logic level 1.
Mode 1: Multiprocessor Communications Enable.
0: Logic level of ninth bit is ignored.
1: RI0 is set and an interrupt is generated only when the ninth bit is logic 1.
Receive Enable.
0: UART0 reception disabled.
1: UART0 reception enabled.
Ninth Transmission Bit.
The logic level of this bit will be sent as the ninth transmission bit in 9-bit UART Mode
(Mode 1). Unused in 8-bit mode (Mode 0).
Ninth Receive Bit.
RB80 is assigned the value of the STOP bit in Mode 0; it is assigned the value of the
9th data bit in Mode 1.
Transmit Interrupt Flag.
Set by hardware when a byte of data has been transmitted by UART0 (after the 8th bit
in 8-bit UART Mode, or at the beginning of the STOP bit in 9-bit UART Mode). When
the UART0 interrupt is enabled, setting this bit causes the CPU to vector to the UART0
interrupt service routine. This bit must be cleared manually by software.
Receive Interrupt Flag.
Set to 1 by hardware when a byte of data has been received by UART0 (set at the
STOP bit sampling time). When the UART0 interrupt is enabled, setting this bit to 1
causes the CPU to vector to the UART0 interrupt service routine. This bit must be
cleared manually by software.
R
6
1
MCE0
R/W
5
0
REN0
R/W
Rev. 1.2
4
0
Function
TB80
R/W
3
0
RB80
R/W
2
0
R/W
TI0
1
0
R/W
RI0
0
0