MC908AP32CBE Freescale Semiconductor, MC908AP32CBE Datasheet - Page 67

• Manufacturer Part Number: MC908AP32CBE
• Description: IC MCU 32K FLASH 8MHZ 42DIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908AP32CBE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, IRSCI, SCI, SPI
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 30
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 42-DIP (0.600", 15.24mm)
• Controller Family/series: HC08
• No. Of I/o's: 30
• Ram Memory Size: 2KB
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC08AP
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Development Tools By Supplier: FSICEBASE, DEMO908AP64E, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Freescale Semiconductor
STX opr
STX opr
STX opr,X
STX opr,X
STX ,X
STX opr,SP
STX opr,SP
SUB #opr
SUB opr
SUB opr
SUB opr,X
SUB opr,X
SUB ,X
SUB opr,SP
SUB opr,SP
SWI
TAP
TAX
TPA
TST opr
TSTA
TSTX
TST opr,X
TST ,X
TST opr,SP
TSX
TXA
TXS
WAIT
Source
Form
Store X in M
Subtract
Software Interrupt
Transfer A to CCR
Transfer A to X
Transfer CCR to A
Test for Negative or Zero
Transfer SP to H:X
Transfer X to A
Transfer H:X to SP
Enable Interrupts; Wait for Interrupt
Operation
Table 4-1. Instruction Set Summary
MC68HC908AP Family Data Sheet, Rev. 4
(A) – $00 or (X) – $00 or (M) – $00
PCH ← Interrupt Vector High Byte
PCL ← Interrupt Vector Low Byte
I ← 0; Inhibit CPU clocking until
SP ← (SP) – 1; Push (PCH)
SP ← (SP) – 1; Push (CCR)
PC ← (PC) + 1; Push (PCL)
SP ← (SP) – 1; Push (X)
SP ← (SP) – 1; Push (A)
SP ← (SP) – 1; I ← 1
(SP) ← (H:X) – 1
H:X ← (SP) + 1
Description
A ← (A) – (M)
CCR ← (A)
A ← (CCR)
interrupted
M ← (X)
X ← (A)
A ← (X)
V H I N Z C
0 – – o o –
– – 1 – – – INH
– – – – – – INH
– – – – – – INH
0 – – o o –
– – – – – – INH
– – – – – – INH
– – – – – – INH
– – 0 – – – INH
o – – o o o
o o o o o o INH
Effect on
CCR
DIR
EXT
IX2
IX1
IX
SP1
SP2
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
DIR
INH
INH
IX1
IX
SP1
9EDF
9EEF
9EE0
9ED0
9E6D
CF
DF
BF
EF
FF
A0
B0
C0
D0
E0
3D
4D
5D
6D
7D
F0
83
84
97
85
95
9F
94
8F
Opcode Map
dd
hh ll
ee ff
ff
ff
ee ff
ii
dd
hh ll
ee ff
ff
ff
ee ff
dd
ff
ff
67
3
4
4
3
2
4
5
2
3
4
4
3
2
4
5
9
2
1
1
3
1
1
3
2
4
2
1
2
1