HD64F3687GFPV Renesas Electronics America, HD64F3687GFPV Datasheet - Page 147

• Manufacturer Part Number: HD64F3687GFPV
• Description: IC H8 MCU FLASH 56K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of HD64F3687GFPV

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 45
• Program Memory Size: 56KB (56K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-LQFP
• Package: 64LQFP
• Family Name: H8
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 45
• Interface Type: I2C/SCI
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 3
• For Use With: R0K436079S000BE - KIT DEV FOR H8/36079 W/COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

2.2.38 (2) MULXS (W)
Notes
MULXS (MULtiply eXtend as Signed)
Operation
ERd
Assembly-Language Format
MULXS.W Rs, ERd
Operand Size
Word
Description
This instruction multiplies the lower 16 bits of a 32-bit register ERd (destination operand) by the
contents of a 16-bit register Rs (source operand) as signed data and stores the result in the 32-bit
register ERd. Rs can be the upper part (Ed) or lower part (Rd) of ERd. The operation performed is
16-bit 16-bit
Available Registers
ERd: ER0 to ER7
Rs:
Operand Format and Number of States Required for Execution
Register direct
Addressing
Mode
R0 to R7, E0 to E7
Rs
Don’t care Multiplicand
ERd
ERd
Mnemonic
32-bit signed multiplication.
MULXS.W
16 bits
Operands
Rs, ERd
Multiplier
16 bits
1st byte
Rs
0
1
Condition Code
H: Previous value remains unchanged.
N: Set to 1 if the result is negative; otherwise
Z: Set to 1 if the result is zero; otherwise
V: Previous value remains unchanged.
C: Previous value remains unchanged.
2nd byte
C
cleared to 0.
cleared to 0.
Instruction Format
— —
Rev. 3.00 Dec 13, 2004 page 131 of 258
I
0
UI
Section 2 Instruction Descriptions
Product
32 bits
— —
H
3rd byte
ERd
5
U
2
N
4th byte
rs
REJ09B0213-0300
Multiply Signed
Z
0 erd
—
V
States
No. of
—
C
24