HD64F3687GFPV Renesas Electronics America, HD64F3687GFPV Datasheet - Page 99

• Manufacturer Part Number: HD64F3687GFPV
• Description: IC H8 MCU FLASH 56K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of HD64F3687GFPV

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 45
• Program Memory Size: 56KB (56K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-LQFP
• Package: 64LQFP
• Family Name: H8
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 45
• Interface Type: I2C/SCI
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 3
• For Use With: R0K436079S000BE - KIT DEV FOR H8/36079 W/COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

2.2.26 (1) DIVXS (B)
DIVXS (DIVide eXtend as Signed)
Operation
Rd ÷ Rs
Assembly-Language Format
DIVXS.B Rs, Rd
Operand Size
Byte
Description
This instruction divides the contents of a 16-bit register Rd (destination register) by the contents of
an 8-bit register Rs (source register) and stores the result in the 16-bit register Rd. The division is
signed. The operation performed is 16 bits ÷ 8 bits
quotient is placed in the lower 8 bits of Rd. The remainder is placed in the upper 8 bits of Rd.
Valid results are not assured if division by zero is attempted or an overflow occurs. For
information on avoiding overflow, see DIVXS Instruction, Zero Divide, and Overflow.
Available Registers
Rd: R0 to R7, E0 to E7
Rs: R0L to R7L, R0H to R7H
Rd
Dividend
16 bits
Rd
Divisor
8 bits
Rs
Condition Code
H: Previous value remains unchanged.
N: Set to 1 if the quotient is negative;
Z: Set to 1 if the divisor is zero; otherwise
V: Previous value remains unchanged.
C: Previous value remains unchanged.
8-bit quotient and 8-bit remainder. The
otherwise cleared to 0.
cleared to 0.
— —
I
Remainder
Rev. 3.00 Dec 13, 2004 page 83 of 258
8 bits
UI
Section 2 Instruction Descriptions
—
H
Rd
Quotient
—
U
8 bits
N
REJ09B0213-0300
Z
Divide Signed
—
V
—
C