HD64F38024DV Renesas Electronics America, HD64F38024DV Datasheet - Page 60

• Manufacturer Part Number: HD64F38024DV
• Description: IC H8/SLP MCU FLASH 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300L SLPr

Specifications of HD64F38024DV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SCI
• Peripherals: LCD, PWM, WDT
• Number Of I /o: 51
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 2 Instruction Set
* Register direct, register indirect, or absolute addressing.
Rev. 2.00 Dec 27, 2004 page 46 of 128
REJ09B0214-0200
2.2.8
Operation
0
Assembly-Language Format
BCLR #xx:3, <EAd>
BCLR Rn, <EAd>
Operand Size
Byte
Description
This instruction clears a specified bit in the destination operand to 0. The bit number can be
specified by 3-bit immediate data, or by the lower three bits of an 8-bit general register. The
destination operand can be located in a general register or memory.
The specified bit is not tested before being cleared. The condition code flags are not altered.
Instruction Formats and Number of Execution States
<EAd>*
Register direct
Register indirect
Absolute address
Register direct
Register indirect
Absolute address
Addressing
mode
(<Bit No.> of <EAd>)
BCLR (bit clear)
Byte data in register or memory
Mnem.
BCLR
BCLR
BCLR
BCLR
BCLR
BCLR
#xx:3, Rd
#xx:3,@Rd
#xx:3,@aa:8
Rn, Rd
Rn, @Rd
Rn, @aa:8
Operands
Condition Code
I: Previous value remains unchanged.
H: Previous value remains unchanged.
N: Previous value remains unchanged.
Z: Previous value remains unchanged.
V: Previous value remains unchanged.
C: Previous value remains unchanged.
Bit No.
1st byte
7
7
7
6
7
7
F
2
D
2
D
F
— — — — — — — —
I
#xx:3 or Rn
0 IMM
0 rd
0 rd
2nd byte
7
rn
abs
abs
Instruction code
H
rd
0
0
rd
3rd byte
0
7
7
6
6
N
2
2
2
2
Z
0
0 IMM
0 IMM
rn
rn
4th byte
V
C
0
0
0
0
No. of
states
2
8
8
2
8
8
BCLR