MC56F8346VFVE Freescale Semiconductor, MC56F8346VFVE Datasheet - Page 116

• Manufacturer Part Number: MC56F8346VFVE
• Description: IC DSP 16BIT 60MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8346VFVE

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 62
• Program Memory Size: 136KB (68K x 16)
• Program Memory Type: FLASH
• Ram Size: 6K x 16
• Voltage - Supply (vcc/vdd): 2.25 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Product: DSPs
• Data Bus Width: 16 bit
• Processor Series: MC56F83xx
• Core: 56800E
• Numeric And Arithmetic Format: Fixed-Point
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 62
• Data Ram Size: 4 KB
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Interface Type: SCI, SPI
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 4 Channel
• Package: 144LQFP
• Family Name: 56F8xxx
• Maximum Speed: 60 MHz
• Number Of Timers: 16
• For Use With: MC56F8367EVME - EVAL BOARD FOR MC56F83X
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6.5.6
Most of the pins on the chip have on-chip pull-up resistors. Pins which can operate as GPIO can have these
resistors disabled via the GPIO function. Non-GPIO pins can have their pull-ups disabled by setting the
appropriate bit in this register. Disabling pull-ups is done on a peripheral-by-peripheral basis (for pins not
muxed with GPIO). Each bit in the register (see
Table 2-2
6.5.6.1
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.5.6.2
This bit controls the pull-up resistors on the FAULTA3 pin.
6.5.6.3
This bit controls the pull-up resistors on the CAN_RX pin.
6.5.6.4
This bit controls the pull-up resistors on the EMI_MODE pin.
6.5.6.5
This bit controls the pull-up resistors on the RESET pin.
6.5.6.6
This bit controls the pull-up resistors on the IRQA and IRQB pins.
6.5.6.7
This bit controls the pull-up resistors on the EXTBOOT pin.
116
Base + $8
RESET
Write
Read
Base + $7
RESET
Read
Write
to identify which pins can deactivate the internal pull-up resistor.
SIM Pull-up Disable Register (SIM_PUDR)
Reserved—Bit 15
PWMA1—Bit 14
CAN—Bit 13
EMI_MODE—Bit 12
RESET—Bit 11
IRQ—Bit 10
XBOOT—Bit 9
15
0
0
15
PWMA1
Figure 6-7 Least Significant Half of JTAG ID (SIM_LSH_ID)
0
0
14
0
Figure 6-8 SIM Pull-up Disable Register (SIM_PUDR)
14
1
1
CAN
13
0
13
0
0
MODE
EMI_
12
0
12
0
0
RESET
11
0
56F8346 Technical Data, Rev. 15
11
0
0
IRQ
10
0
10
0
0
XBOOT PWMB PWMA0
Figure
9
0
9
0
0
6-8) corresponds to a functional group of pins. See
8
0
8
0
0
7
0
7
0
0
6
0
0
6
0
0
CTRL
5
0
0
5
0
4
1
1
4
0
0
JTAG
3
3
0
1
1
Freescale Semiconductor
2
1
1
2
0
0
1
0
0
1
0
0
Preliminary
0
1
1
0
0
0