MCF53012CQT240 Freescale Semiconductor, MCF53012CQT240 Datasheet

Page 1

... UARTs 2 • bus interface This document contains information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2010. All rights reserved. Preliminary—Subject to Change Without Notice Document Number: MCF53017 Rev. 5, 3/2010 MCF53017 LQFP–208 MAPBGA– ...

Page 2

... Handset Amplifier . . . . . . . . . . . . . . . . . . . . . . . 56 5.20.3 Headphone Amplifier . . . . . . . . . . . . . . . . . . . . 57 5.20.4 Microphone Amplifier . . . . . . . . . . . . . . . . . . . . 57 5.21 JTAG and Boundary Scan Timing . . . . . . . . . . . . . . . . 58 5.22 Debug AC Timing Specifications . . . . . . . . . . . . . . . . . 60 6 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 7 Product Documentation Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 MCF5301x Data Sheet, Rev. 5 Preliminary—Subject to Change Without Notice 2 C Input/Output Timing Specifications . . . . . . . . . . . . 35 Freescale Semiconductor ...

Page 3

... EMAC – Enchanced multiply-accumulate unit EPORT – Edge port module FEC – Fast Ethernet Controller GPIO – General purpose input/output module – Inter-Integrated Circuit Freescale Semiconductor MCF53017 BDM 2 FECs CAU eDMA Crossbar Switch (XBS) Peripheral Bridge Smart Card IIM DSPI Interface RTC & ...

Page 4

... Freescale Semiconductor • • • • • • • • • • • • • • • 4 • 4 • 2 ...

Page 5

... General purpose I/O Module (GPIO) ® JTAG - IEEE 1149.1 Test Access Port Package 2 Ordering Information Freescale Part Number MCF53010CQT240 MCF53010 Microprocessor MCF53011CQT240 MCF53011 Microprocessor MCF53012CQT240 MCF53012 Microprocessor MCF53013CQT240 MCF53013 Microprocessor MCF53014CMJ240J MCF53014 Microprocessor MCF53015CMJ240J MCF53015 Microprocessor MCF53016CMJ240J MCF53016 Microprocessor MCF53017CMJ240J MCF53017 Microprocessor ...

Page 6

... Power Filter DD NOTE (EV ), SDRAM and EV is non-critical during power-up and power-down sequences are specified relative MCF5301x Data Sheet, Rev. 5 Preliminary—Subject to Change Without Notice PLL V Pin DD 0.1 µF Figure 2 should be USB V Pin DD 0.1 µF (SDV ), PLL V (PV ), and internal logic / Freescale Semiconductor ...

Page 7

... ESD protection diodes. There are no requirements for the fall times of the power supplies. The recommended power down sequence is as follows: 1. Drop IV / Drop EVDD/SDVDD supplies. Freescale Semiconductor Supplies Stable 2 , SDV more than 0.4V at any time, including power-up should track EV /SDV ...

Page 8

... Current measured at maximum system clock frequency, all modules active, and default drive strength with matching load 120 Core Frequency (MHz) Symbol 1 MCF5301x Data Sheet, Rev. 5 Preliminary—Subject to Change Without Notice 160 200 240 Typical Max Unit — TBD mW — TBD mW — TBD — 82 — TBD mA — TBD mA — TBD mA Freescale Semiconductor ...

Page 9

... The primary functionality of a pin is not necessarily its default functionality. Most pins that are muxed with GPIO will default to their GPIO functionality. See exceptions. Table 5. Special-Case Default Signal Functionality Freescale Semiconductor 240VCO, 120MHz 480VCO, 120MHz core core 28 ...

Page 10

... SDVDD 197, 166, 179, 178 — O SDVDD — — O SDVDD 5 — O SDVDD 6 — O SDVDD SDVDD 3 — O SDVDD 2 — O SDVDD 4 — O SDVDD 206 Freescale Semiconductor MCF53014 MCF53015 MCF53016 MCF53017 256 MAPBGA J5, G5 P16, N16 R15, R14 N13, R12, R13 N12 D13 A4, B12, C9 ...

Page 11

... IRQ1FEC[3:2] PIRQ1FEC[3:2] IRQ1FEC[1:0] PIRQ1FEC[1:0] IRQ07 PIRQ07 IRQ06 PIRQ06 IRQ04 PIRQ04 IRQ01 PIRQ01 SDHC_DAT3 PSDHC5 SDHC_DAT[2:0] PSDHC[4:2] SDHC_CMD PSDHC1 SDHC_CLK PSDHC0 Freescale Semiconductor Alternate 1 Alternate 2 — — — — — — — — — — — — — — — — — ...

Page 12

... I/O EVDD — O EVDD — — O EVDD — — — O EVDD — O EVDD — — O USB 148 VDD — O USB 149 VDD Freescale Semiconductor MCF53014 MCF53015 MCF53016 MCF53017 256 MAPBGA P10 E14 D16 E13 E15 F13 L3 M2 F16 L14 M16 ...

Page 13

... SSI_RXD PSSI4 SSI_TXD PSSI3 SSI_FS PSSI2 SSI_MCLK PSSI1 SSI_BCLK PSSI0 I2C_SCL PFECI2C1 I2C_SDA PFECI2C0 DSPI_PCS3 PDSPI6 DSPI_PCS2 PDSPI5 Freescale Semiconductor Alternate 1 Alternate 2 USB Host — — — — FEC 1 — MII0_TXER — MII0_COL FEC 0 — MII0_RXDV — MII0_RXD[1:0] — MII0_RXER — ...

Page 14

... EVDD 12 — I EVDD 122 — I EVDD 121 — O EVDD EVDD 64 — I EVDD EVDD 66 — O EVDD 120 U I EVDD 119 U I EVDD 118 Freescale Semiconductor MCF53014 MCF53015 MCF53016 MCF53017 256 MAPBGA F14 G13 H13 E16 F15 K13 L16 — M15 M14 L15 ...

Page 15

... IRQ1FECn pin takes priority. The corresponding IRQ1DEBUGn pin is disconnected internally from the edge port 1 module. 5 GPIO functionality is determined by the edge port module. The GPIO module is only responsible for assigning the alternate functions JTAG_EN is asserted, these pins default to alternate 1 (JTAG) functionality. The GPIO module is not responsible for assigning these pins. Freescale Semiconductor Alternate 1 Alternate 2 Test — ...

Page 16

... RMII1_MDIO 24 EVDD 25 VSS 26 EVDD 27 U0RXD 28 U0TXD 29 IRQ17 30 IRQ16 31 IRQ15 32 IRQ14 33 IRQ13 34 IRQ12 35 IRQ11 36 IRQ10 37 I2C_SCL 38 I2C_SDA 39 VSS 40 EVDD 41 RESET 42 RSTOUT 43 ALLPST 44 IVDD 45 VSS 46 VDD_OSC 47 EVDD 48 VSS 49 EXTAL 50 XTAL 51 EVDD VSS 52 MCF5301x Data Sheet, Rev. 5 Preliminary—Subject to Change Without Notice Freescale Semiconductor ...

Page 17

... Figure 6. MCF53010, MCF53011, MCF53012, and MCF53013 Pinout Top View, Right (208 QFP) Freescale Semiconductor 156 SDVDD 155 SD_CS0 154 SD_CAS 153 FB_CLK 152 SD_RAS 151 SD_CKE 150 SD_WE 149 USBO_DP 148 USBO_DM 147 VDD_USBO 146 TEST 145 SIM1_PD 144 SIM1_RST 143 ...

Page 18

... FB_A4 FB_A10 FB_A13 FB_A20 CODEC CODEC FB_A5 FB_A9 FB_A16 FB_A17 _ADCN FB_A2 FB_A6 FB_A12 FB_A11 FB_A14 AVSS_ SPKR_ FB_A1 FB_A0 FB_A3 FB_A8 Freescale Semiconductor 15 16 SD_CS VSS A SD_ USBO_ B CKE DP SD_ USBO_ C RAS DM SD_ SIM1_ D CAS VEN SIM1_ DSPI_ E PD SIN ...

Page 19

... Insure external EV injection current. This will be the greatest risk when the MCU is not consuming power (ex; no clock). Power supply must maintain regulation within operating EV instantaneous and operating maximum current conditions. Freescale Semiconductor NOTE Table 7. Absolute Maximum Ratings Symbol ...

Page 20

... JMA MCF5301x Data Sheet, Rev. 5 Preliminary—Subject to Change Without Notice 256 208 MAPBGA LQFP 1,2 1,2 ° JMA 1,2 1,2 ° JMA ° ° 1,5 1,5 ° 105 105 j and T ( neglected Freescale Semiconductor Unit o C Eqn. 1 Eqn. 2 Eqn. 3 ...

Page 21

... SDR/Bus Pad Supply Voltage (nominal 3.3V) SDRAM and FlexBus Input Low Voltage Mobile DDR/Bus Input High Voltage (nominal 1.8V) DDR/Bus Pad Supply Voltage (nominal 2.5V) SDR/Bus Pad Supply Voltage (nominal 3.3V) Freescale Semiconductor and T can be obtained by solving D J Table 9. ESD Protection Characteristics ...

Page 22

... SDV – 0.35 — DD 2.9 — SDV OL × 0.1 — SDV DD — 0.35 — 0.4 I –2.5 2 315 APU I 25 150 APU C in — 7 — 7 pins. The filter shown in DD PLL V Pin DD Figure 2 should be Freescale Semiconductor Unit V V μA μA μA pF ...

Page 23

... The recommended power down sequence is as follows: 1. Drop IV /PLLV Drop EV /SDV supplies Freescale Semiconductor 0 Ω µF GND Figure 9. USB V Power Filter DD NOTE is non-critical during power-up and power-down sequences. Both SDV then the sense circuits in the I/O pads will cause all pad output drivers ...

Page 24

... See crystal L spec 2 × C — – L_XTAL L C – S_XTAL 7 C PCB_XTAL 2 × C — – – S_EXTAL 7 C PCB_EXTAL C jitter — TBD — TBD C 0.8 2.2 mod f 200 667 vco Freescale Semiconductor Unit MHz MHz MHz MHz sys sys/3 %f sys/3 MHz ...

Page 25

... ROMs, flash memories, gate-array logic, or other simple target (slave) devices with little or no additional circuitry. For asynchronous devices a simple chip-select based interface can be used. The FlexBus interface has six general purpose chip-selects (FB_CS[5:0]) which can be configured to be distributed between the FlexBus or SDRAM memory interfaces. Freescale Semiconductor , EV , and V ...

Page 26

... Preliminary—Subject to Change Without Notice Symbol Min Max Unit — 80 Mhz t 12.5 — ns FBCK t — 7.0 ns FBCHDCV t 1 — ns FBCHDCI t 3.5 — ns DVFBCH t 0 — ns DIFBCH t 4 — ns CVFBCH t 0 — ns CIFBCH Section 5.7.2, “DDR SDRAM AC Timing Freescale Semiconductor Notes f sys/3 t cyc ...

Page 27

... SDR mode on write cycles and relative to SD_DQS on read cycles. The device’s SDRAM controller is a DDR controller that has an SDR mode. Because it is designed to support DDR, a DQS pulse must still be supplied to the device for each data beat of an SDR read. The processor accomplishes this by asserting a signal named SD_SDR_DQS during Freescale Semiconductor S0 S1 ...

Page 28

... SD_CLK 0.5 × SD_CLK — 1.0 2.0 — ns — Self timed ns 0.25 × 0.40 × SD_CLK ns SD_CLK Does not apply. 0.5×SD_CLK fixed width. 0.25 × — ns SD_CLK 1.0 — ns 0.75 × SD_CLK — 0.5 1.5 — ns Freescale Semiconductor Notes ...

Page 29

... SDDM SD_SDR_DQS (Measured at Output Pin) SD_DQS[3:2] (Measured at Input Pin) Delayed SD_CLK D[31:0] from Memories NOTE: Data driven from memories relative to delayed memory clock. Freescale Semiconductor SD5 COL SD11 SD12 WD1 WD2 Figure 13. SDR Write Timing SD1 SD5 3/4 MCLK Reference COL ...

Page 30

... SD_CLK 0.45 0.55 SD_CLK 0.5 × SD_CLK — 1.0 2.0 — ns — 1.25 SD_CLK 1.5 — ns 1.0 — ns — — 0.5ns 0.5 — ns 0.9 1.1 SD_CLK 0.4 0.6 SD_CLK 0.25 — SD_CLK 0.4 0.6 SD_CLK Freescale Semiconductor Notes ...

Page 31

... SD_CLK Figure 15. SD_CLK and SD_CLK Crossover Timing SD_CLK SD_CLK SD_CSn,SD_WE, SD_RAS, SD_CAS DD4 A[13:0] DM3/DM2 SD_DQS3/SD_DQS2 D[31:24]/D[23:16] Freescale Semiconductor DD1 DD2 DD5 CMD DD6 ROW COL WD1 WD2 WD3 WD4 Figure 16. DDR Write Timing MCF5301x Data Sheet, Rev. 5 Preliminary—Subject to Change Without Notice ...

Page 32

... CL=2 CL=2.5 DD9 DQS Read DQS Read Postamble Preamble DD10 WD1 WD2 WD3 WD4 DQS Read Preamble WD1 WD2 WD3 WD4 1 Symbol Min Max t — 10 CHPOV t 1.5 — CHPOI t 9 — PVCH 1.5 — t CHPI Freescale Semiconductor DQS Read Postamble Unit ...

Page 33

... During low power STOP, the synchronizers for the RESET input are bypassed and RESET is asserted asynchronously to the system. Thus, RESET must be held a minimum of 100 ns. FB_CLK RESET RSTOUT Configuration Overrides*: (RCON, Override pins]) Figure 19. RESET and Configuration Override Timing Refer to the CCM chapter of the MCF5301x Reference Manual for more information. Freescale Semiconductor Figure 18. GPIO Timing Characteristic NOTE MCF5301x Data Sheet, Rev ...

Page 34

... Preliminary—Subject to Change Without Notice 1 Min Max Units Notes 8 × — ns SYS 45% 55% t MCLK 8 × — ns SYS 45% 55% t BCLK — — ns — –2 — — — Min Max Units Notes 8 × t — ns SYS 45% 55% t BCLK 10 — — ns — — — — ns Freescale Semiconductor ...

Page 35

... I C Input/Output Timing Specifications 2 Table 19 lists specifications for the I Table 19. I Num I1 Start condition hold time I2 Clock low period I3 I2C_SCL/I2C_SDA rise time (V I4 Data hold time Freescale Semiconductor S10 Figure 20. SSI Timing — Master Modes S11 S12 S12 S13 S15 S16 ...

Page 36

... Preliminary—Subject to Change Without Notice Min Max Units — — t cyc 0 — — t cyc 2 — t cyc Figure 22. Min Max Units 6 — t cyc 10 — t cyc — — µs 7 — t cyc — — t cyc 2 — t cyc 20 — t cyc 10 — t cyc 2 Table 20. The I C interface Freescale Semiconductor ...

Page 37

... Transmit Signal Timing Specifications Num Characteristic E5 TXCLK to TXD[n:0], TXEN, TXER invalid E6 TXCLK to TXD[n:0], TXEN, TXER valid E7 TXCLK pulse width high E8 TXCLK pulse width low 1 In MII mode RMII mode Freescale Semiconductor Table 21. Receive Signal Timing MII Mode Min Max 1 5 — — 35% 65% ...

Page 38

... Table 23. MII Transmit Signal Timing Characteristic E9 Figure 25. MII Async Inputs Timing Diagram Symbol MCF5301x Data Sheet, Rev. 5 Preliminary—Subject to Change Without Notice E7 E5 Min Max Unit 1.5 — TXCLK period Min Max Unit t 400 — ns MDC MDC — 375 ns 25 — — — ns Freescale Semiconductor ...

Page 39

... DSPI_SCK to DSPI_SOUT valid DS6 DSPI_SCK to DSPI_SOUT invalid DS7 DSPI_SIN to DSPI_SCK input setup DS8 DSPI_SCK to DSPI_SIN input hold Slave Mode DS9 DSPI_SCK to DSPI_SOUT valid Freescale Semiconductor E10 E11 E11 E12 Valid Data E14 Valid Data Characteristic Table 26 provides DSPI timing characteristics for classic SPI timing modes. Refer ...

Page 40

... DS3 DS2 DS2 DS7 DS8 First Data Data DS6 First Data Data MCF5301x Data Sheet, Rev. 5 Preliminary—Subject to Change Without Notice 1 (continued) Min Max Unit 0 — — — ns — — DS4 DS1 Last Data DS5 Last Data Freescale Semiconductor Notes ...

Page 41

... This section describes the electrical information of the eSDHC. 5.16.1 eSDHC Timing Figure 29 depicts the timing of eSDHC, and SDHC_CLK Output from eSDHC to card SDHC_CMD SDHC_DAT[3:0] Input from card to eSDHC SDHC_CMD SDHC_DAT[3:0] Freescale Semiconductor DS2 DS2 DS13 DS10 First Data Data DS11 DS12 First Data Data Table 29 lists the eSDHC timing characteristics ...

Page 42

... Min Max 400 100 400 — — — 3 TLH t — 3 THL t – — ISU t 0 — IH Unit Condition/Remark + 0 3.6 V for high voltage cards, must provide this voltage for card initialization V for low voltage cards Freescale Semiconductor Unit kHz MHz MHz kHz ...

Page 43

... SIM module are asynchronous to each other. There are no required timing relationships between the signals in normal mode. However, there are some in reset and power down sequences. 5.17.1 General Timing Requirements Figure 30 shows the timing of the SIM module, and SIM_CLK Freescale Semiconductor Design Min Max Value — — ...

Page 44

... S rise S fall S trans Figure 31): Response 400 clock cycles < Figure 32): MCF5301x Data Sheet, Rev. 5 Preliminary—Subject to Change Without Notice Min Max 0.01 5 (Some new cards may reach 10) – 20 – 20 – < 200 clock cycles 2 < 40,000 clock cycles Freescale Semiconductor Unit MHz ...

Page 45

... Table 30. Timing Requirements for Power Down Sequence Num Description 1 SIM reset to SIM clock stop 2 SIM reset to SIM TX data low 3 SIM reset to SIM Voltage Enable Low 4 SIM Presence Detect to SIM reset Low Freescale Semiconductor 3 T1 400 clock cycles < 400,000 clock cycles < Figure 33 and Table 30 Symbol S rst2clk ...

Page 46

... The voice codec is powered down when not enabled for power consumption. 46 Srst2clk Srst2dat Srst2ven Symbol t program MCF5301x Data Sheet, Rev. 5 Preliminary—Subject to Change Without Notice Min Max 125 — Freescale Semiconductor Unit µs ...

Page 47

... PCM words 8.1 kHz rate. Following the A/D converter, the signal is digitally filtered, low-pass, and selectable high-pass. Parameter Power Supply Rejection Ratio with respect to 2 AVDD (CODEC_REGBYP) Peak Input Tx AC Input Impedance Absolute Gain Freescale Semiconductor Condition VCLK[2:0]=0 VCLK[2:0]=1,2 VCLK[2:0]=3 VCLK[2:0]=4 VCLK[2:0]=5 VCLK[2:0]=6 VCLK[2:0]=7 No Load, AVDD (CODEC_REGBYP ...

Page 48

... Freescale Semiconductor ...

Page 49

... Small frequency response deviation from straight line in the 60:200 Hz range is acceptable by spec requirements. 8 Small frequency response deviation from straight line in the 3400:4000 Hz range is acceptable by spec requirements. 9 Small frequency response deviation from straight line in the 3400:4000 Hz range is acceptable by spec requirements. Freescale Semiconductor Condition 500Hz < f < 600Hz 600Hz < f < 800Hz 800Hz < f < 1kHz 1kHz < ...

Page 50

... SYNC +0.5dB @ 3.0kHz 70 100 200 300 400 500 700 Hz (VCIHPF=0, LPF Alone Without HPF) MCF5301x Data Sheet, Rev. 5 Preliminary—Subject to Change Without Notice +0.1dB @ 3.4kHz -0.5dB @ 3.0kHz -1.0dB @ 3.4kHz -14dB @ 4.0kHz -35dB @ 4.6kHz 1000 2000 3000 4000 5000 8000 Freescale Semiconductor ...

Page 51

... The input signal for the voice-decoding function is in linear 16-bit two’s compliment PCM words kHz or 8.1 kHz rate. Table 34 shows the voice decoding specifications. Parameter Output Level Output Source Impedance Output Power Supply Rejection Ratio Absolute Gain Gain vs. Signal Freescale Semiconductor +0.5dB @ 300Hz -0.5dB @ 200Hz -0.5dB @ 300Hz -8.0dB @ 200Hz 100 200 300 400 500 700 ...

Page 52

... Freescale Semiconductor ...

Page 53

... Small frequency response deviation from straight line in the 60:200 Hz range is acceptable by spec requirements. 5 Small frequency response deviation from straight line in the 3400:4000 Hz range is acceptable by spec requirements. 6 Small frequency response deviation from straight line in the 3400:4000 Hz range is acceptable by spec requirements. Freescale Semiconductor Condition 500Hz < f < 600Hz 600Hz < f < 800Hz 800Hz < f < 1kHz 1kHz < ...

Page 54

... Figure 36. Voice Signal Frequency Response Requirements at the DAC Path 54 +0.5dB @ 3.0kHz 70 100 200 300 400 500 700 1000 Hz (VCOHPF=0, LPF Alone Without HPF) MCF5301x Data Sheet, Rev. 5 Preliminary—Subject to Change Without Notice +0.1dB @ 3.4kHz -0.5dB @ 3.0kHz -0.8dB @ 3.4kHz -14dB @ 4.0kHz -35dB @ 4.6kHz 2000 300040005000 8000 Freescale Semiconductor ...

Page 55

... The speaker amplifier boosts the power from the DAC and drives the speaker. It also provides analog volume control to optimize the noise performance of the entire channel. Parameter Quiescent Current Shutdown Current Input Reference Offset Max Output Power Total Harmonic Distortion (THD) Integrated Output Noise Freescale Semiconductor -0.5dB @ 200Hz -0.5dB @ 300Hz -8.0dB @ 200Hz 100 200 ...

Page 56

... Freescale Semiconductor Units Units μ μ ...

Page 57

... The microphone amplifier boosts the signal from the microphone and provides it to the ADC. The gain control present in the microphone amplifier helps in optimizing the noise performance of the entire channel. microphone amplifier. Table 38. Microphone Amplifier Specifications Parameter Quiescent Current Shutdown Current Input Reference Offset Freescale Semiconductor Table 37 shows the specifications for the microphone amplifier. Conditions F = 1kHz, THD 16Ω in ...

Page 58

... Symbol Min Max Unit f DC 1/4 f JCYC t 4 — t JCYC t 26 — JCW JCRF t 4 — BSDST t 26 — BSDHT BSDV BSDZ t 4 — TAPBST t 10 — TAPBHT Freescale Semiconductor Units % μ kΩ sys/3 CYC ...

Page 59

... JTAG_EN is expected static signal. Hence, specific timing is not associated with it TCLK (input) J4 TCLK V IL Data Inputs Data Outputs Data Outputs Data Outputs Freescale Semiconductor Figure 38. Test Clock Input Timing J5 Input Data Valid Figure 39. Boundary Scan (JTAG) Timing MCF5301x Data Sheet, Rev. 5 Preliminary— ...

Page 60

... Table 40. Debug AC Timing Specification Characteristic Min 1.5 — 1 MCF5301x Data Sheet, Rev. 5 Preliminary—Subject to Change Without Notice V IH J10 Output Data Valid Output Data Valid Figure 42. Max Units 1.5 t SYS 3.0 ns — ns — PSTCLK — PSTCLK — PSTCLK — PSTCLK Freescale Semiconductor ...

Page 61

... MCF53014 MCF53015 MCF53016 MCF53017 7 Product Documentation Documentation is available from a local Freescale distributor, a Freescale sales office, the Freescale Literature Distribution Center, or through the Freescale world-wide web address at http://www.freescale.com/coldfire. Freescale Semiconductor D0 D1 Figure 42. Real-Time Trace AC Timing D5 Current D4 Past Figure 43. BDM Serial Port AC Timing Table 41 ...

Page 62

... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...