SAK-XC2267-56F66L AC Infineon Technologies, SAK-XC2267-56F66L AC Datasheet - Page 108

• Manufacturer Part Number: SAK-XC2267-56F66L AC
• Description: IC MCU 16BIT FLASH PG-LQFP-100
• Manufacturer: Infineon Technologies
• Series: XC22xxr

Specifications of SAK-XC2267-56F66L AC

• Core Processor: C166SV2
• Core Size: 16/32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, I²C, LIN, SPI, SSC, UART/USART, USI
• Peripherals: DMA, I²S, POR, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 34K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x8/10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: KX226756F66L34ACXT; SAK-XC2267-56F66L34 AC; SAK-XC2267-56F66L34ACINTR; SAK-XC2267-56F66L34ACINTR; SAK-XC2267-56F66LACINTR; SP000300104

4.6.5
The following parameters are applicable for a USIC channel operated in SSC mode.
Note: These parameters are not subject to production test but verified by design and/or
Table 31
Parameter
Master Mode Timing
Slave select output SELO active
to first SCLKOUT transmit edge
Slave select output SELO inactive
after last SCLKOUT receive edge
Transmit data output valid time
Receive data input setup time to
SCLKOUT receive edge
Data input DX0 hold time from
SCLKOUT receive edge
Slave Mode Timing
Select input DX2 setup to first
clock input DX1 transmit edge
Select input DX2 hold after last
clock input DX1 receive edge
Data input DX0 setup time to
clock input DX1 receive edge
Data input DX0 hold time from
clock input DX1 receive edge
Data output DOUT valid time
1) The maximum value further depends on the settings for the slave select output leading delay.
2)
3) The maximum value depends on the settings for the slave select output trailing delay and for the shift clock
4) These input timings are valid for asynchronous input signal handling of slave select input, shift clock input, and
Data Sheet
t
output delay.
receive data input (bits DXnCR.DSEN = 0).
SYS
characterization.
= 1/
f
SYS
Synchronous Serial Interface Timing
(= 12.5 ns @ 80 MHz)
SSC Master/Slave Mode Timing for Upper Voltage Range
(Operating Conditions apply),
Symbol
t
t
t
t
t
t
t
t
t
t
1
2
3
4
5
10
11
12
13
14
CC
CC
CC
SR
SR
SR
SR
SR
SR
CC
106
Min.
0
0.5 ×
t
-6
31
-7
7
5
7
5
8
BIT
C
L
= 50 pF
Values
Typ.
–
–
–
–
–
–
–
–
–
–
XC2000 Family Derivatives
Max.
1)
3)
13
–
–
–
–
–
–
29
Electrical Parameters
XC2267 / XC2264
Unit Note /
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
V2.1, 2008-08
Test Co
ndition
2)
4)
4)
4)
4)
4)