SAK-TC1762-128F80HL AC Infineon Technologies, SAK-TC1762-128F80HL AC Datasheet - Page 99

• Manufacturer Part Number: SAK-TC1762-128F80HL AC
• Description: IC MCU 32BIT FLASH PG-LQFP-176
• Manufacturer: Infineon Technologies
• Series: TC17xxr

Specifications of SAK-TC1762-128F80HL AC

• Core Processor: TriCore
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: ASC, CAN, MLI, MSC, SSC
• Peripherals: DMA, POR, WDT
• Number Of I /o: 81
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 52K x 8
• Voltage - Supply (vcc/vdd): 1.42 V ~ 1.58 V
• Data Converters: A/D 2x10b; A/D 32x8b,10b,12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 176-LFQFP
• Packages: PG-LQFP-176
• Max Clock Frequency: 80.0 MHz
• Sram (incl. Cache): 52.0 KByte
• Can Nodes: 2
• A / D Input Lines (incl. Fadc): 36
• Program Memory: 1.0 MB
• For Use With: B158-H8539-G2-X-7600IN - KIT STARTER TC176X SERIES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: KT1762128F80HLACXT; SAK-TC1762-128F80HLACINTR; SP000318061

Preliminary
4.3.5
Section 4.3.5
TC1762.
Note: All PLL characteristics defined on this and the next page are verified by design
Table 4-13
Parameter
Accumulated jitter
VCO frequency range
PLL base frequency
PLL lock-in time
1) The CPU base frequency which is selected after reset is calculated by dividing the limit values by 16 (this is
Phase Locked Loop Operation
When PLL operation is enabled and configured, the PLL clock
clock
and
clock outputs TRCLK and SYSCLK (P4.3) which are derived from the PLL clock
There are two formulas that define the (absolute) approximate maximum value of jitter
D
number
K : K-Divider Value
P : Number of
D
f
Data Sheet
P K 900
P K 900
CPU
P
P
×
×
the K factor after reset).
: Jitter in ns
in ns dependent on the K-factor, the CPU clock frequency
f
: CPU frequency in MHz
SYS
f
characterization.
<
≥
CPU
P
is defined by:
) is constantly adjusted to the selected frequency. The relation between
of consecutive
Phase Locked Loop (PLL)
PLL Parameters (Operating Conditions apply)
provides the characteristics of the PLL parameters and its operation in the
f
CPU
Dp ns
Dp ns
periods
1)
[
[
]
]
f
VCO
=
=
f
CPU
±
±
= K ×




clock periods.
-----------------------------
fcpu MHz
--------------------------------------- -
fcpu MHz
5 P
f
[
[
CPU
×
4500
. The PLL causes a jitter of
]
] K
+
×
Symbol
D
f
f
t
95
VCO
PLLBASE
L
0 9 ,
P
+


0 9 ,


Min.
See
400
500
600
140
150
200
–
Limit Values
Figure 4-12
f
VCO
Electrical Parameters
f
Max.
500
600
700
320
400
480
200
CPU
(and with it the CPU
f
CPU
in MHz, and the
and affects the
V1.0, 2008-04
Unit
–
MHz
MHz
MHz
MHz
MHz
MHz
µs
TC1762
f
VCO
(4.1)
(4.2)
f
VCO
.