DSPIC30F6011-30I/PF Microchip Technology, DSPIC30F6011-30I/PF Datasheet
DSPIC30F6011-30I/PF
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DSPIC30F6011-30I/PF Summary of contents
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... ICD Product ID Running ICD Self Test ...Passed MPLAB ICD 2 Ready The errata described in this section will be addressed in future revisions of dsPIC30F6011, dsPIC30F6012, dsPIC30F6013 and dsPIC30F6014 silicon. Silicon Errata Summary The following list summarizes the errata described in this document: 1. ...
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... DD 20. dsPIC30F6011/6013 Code Protection Addresses in the range 0x6000 through 0xFFFF may not be code-protected for this revision of dsPIC30F6011 and dsPIC30F6013 silicon. 21. 4x PLL Operation The 4x PLL mode of operation may not function correctly for certain input frequencies. 22. Sequential Interrupts Sequential interrupts after modifying the CPU IPL, interrupt IPL, interrupt enable or interrupt flag may cause an address error trap ...
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... MCU Multiply instruction, MUL.UU. © 2008 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 3. Module: MAC class Instructions with +4 Sequential MAC class instructions, which prefetch data from Y data space using +4 address modification, will cause an address error trap. The trap occurs only when all of the following conditions are true: 1 ...
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... Example 2 is demonstrated in Example 3. DS80198J-page 4 These instructions are identified in Table 1. Example 2 demonstrates a scenario where this occurs. Also, always use Work around 2 if the C compiler is used dsPIC30F6011/6012/6013/6014 devices. (2) Examples of Incorrect Operation ADDC W0, [W1++], W2 ; SUBB.b W0, [++W1 SUBBR.b W0, [++W1 CPB W0, [W1++], W4 ; RLC [W1 RRC [W1 ...
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... Error ;trap flag bit reset ;Software reset © 2008 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 8. Module: Y Data Space Dependency When an instruction that writes to a location in the address range of Y data memory (addresses between 0x1800 and 0x27FF) is immediately followed by a MAC type DSP instruction that reads a location also resident in Y data memory, the two operations will not be executed as specified ...
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... Module: Interrupt Controller –Traps Catastrophic accumulator overflow traps are enabled as follows: - COVTE (INTCON1<8> SATA/SATB (CORCON <7:6> carry generated out of bit 39 in the accumulator causes a catastrophic overflow of the accumulator since the sign bit has been destroyed math error trap handler has been defined, the processor will vector to the math error trap handler upon a catastrophic overflow ...
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... Work around None. The application may only use the 1:1 prescaler for 32-bit timers. © 2008 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 13. Module: Output Compare A glitch will be produced on an output compare pin under the following conditions: • The user software initially drives the I/O pin high using the output compare module or a write to the associated PORT register ...
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... Module: 12-bit 100 ksps ADC Input channel scanning allows the ADC to acquire and convert signals on a selected set of “MUX A” input pins in sequence. This function is controlled by the CSCNA (ADCON2<10>) bit and the ADCSSL SFR. The ALTS (ADCON2<0>) bit, when set, allows the ADC to alternately acquire and convert a “ ...
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... Data loaded into TXBUF0 contains 15 MSbs of the actual 16-bit data to be transmitted, while the MSb of TXBUF0 is cleared. 4: Not all serial clock pulses are shown in this timing diagram. © 2008 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 Frame Synch and first data bit sampled here LSB LSB ...
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... Module: Data Converter Interface – Idle For this release of silicon, the DCI module should not be stopped when the device enters Idle mode. Work around Do not set the DCISIDL (DCICON1<13>) bit. This will ensure the DCI module continues to run when the device enters Idle mode. ...
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... Note: Applications that use the CAN peripherals and data EEPROM should also refer to Errata module 1 and 17. 20. Module: dsPIC30F6011/dsPIC30F6013 Code Protection Addresses in the range, 0x6000 through 0xFFFF, may not be code-protected for this revision of dsPIC30F6011 and dsPIC30F6013 silicon. Work around None. 21. Module: 4x PLL Operation When the 4x PLL mode of operation is selected, the specified input frequency range of 4-10 MHz is not fully supported ...
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... Module: Interrupt Controller – Sequential Interrupts When interrupt nesting is enabled (or NSTDIS (INTCON1<15>) bit is ‘0’), the following sequence of events will lead to an address error trap. The generic terms “Interrupt 1” and “Interrupt 2” are used to represent any two enabled dsPIC30F interrupts ...
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... Module: 8x PLL Mode If 8x PLL mode is used, the input frequency range is 5-10 MHz instead of 4-10 MHz. Work around None PLL is used, ensure that the input crystal or clock frequency is 5 MHz or greater. © 2008 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 \ \ \ \ DS80198J-page 13 ...
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... Module: Sleep Mode Execution of the Sleep instruction (PWRSAV #0) may cause incorrect program operation after the device wakes up from Sleep. The current consumption during Sleep may also increase beyond the specifications listed in the device data sheet. Work arounds To avoid this issue, any of the following three work arounds can be implemented, depending on the application requirements ...
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... Note: The above work around is recommended for users for whom application hardware changes are not possible. © 2008 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 Work around 3: Instead of executing a PWRSAV #0 instruction to put the device into Sleep mode, perform a clock switch to the 32 kHz Low-Power (LP) Oscillator with a 64:1 postscaler mode ...
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... Module When the I C module is configured as a slave, either in single-master or multi-master mode, the receiver buffer is filled whether a valid slave address is detected or not. Therefore receiver overflow condition occurs and this condition is indicated by the I2COV flag in the I2CSTAT register. This overflow condition inhibits the ability to set the ...
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... Status bit (OSCCON<3>). If this bit is clear, return from the trap service routine immediately and continue program execution. © 2008 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 30. Module: PSV Operations An address error trap occurs in certain addressing modes when accessing the first four bytes of an PSV page. This only occurs when using the following addressing modes: • ...
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... Module When the I C module is enabled by setting the I2CEN bit in the I2CCON register, the dsPIC DSC device generates a glitch on the SDA and SCL pins. This glitch falsely indicates “Communication 2 Start” to all devices on the I C bus, and can cause a bus collision in a multi-master configuration ...
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... Port – Port Pin Multiplexed with IC1). Revision H (5/2008) 2 Added silicon issues 28 and 29 (I C), and 30 (Timer). Revision J (9/2008) 2 Replaced issues 25 and with issue 33 (I Added silicon issues 29 (PLL Lock Status Bit), 30 (PSV 2 Operations) and 31-33 (I C). © 2008 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 2 C), and 27 (I/O 2 C). DS80198J-page 19 ...
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... NOTES: DS80198J-page 20 © 2008 Microchip Technology Inc. ...
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... PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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