DSPIC30F6011-30I/PF Microchip Technology, DSPIC30F6011-30I/PF Datasheet
DSPIC30F6011-30I/PF
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DSPIC30F6011-30I/PF Summary of contents
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... Device and Revision IDs listed in Table 1. The silicon issues are summarized in Table 2. The errata described in this document will be addressed in future revisions of the dsPIC30F6011/6012/6013/ 6014 silicon. Note: This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current ...
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... TABLE 2: SILICON ISSUE SUMMARY Item Module Feature Number Data Speed 1. EEPROM CPU Unsigned 2. MAC Instruction CPU MAC class 3. Instructions with +4 Address Modification CPU 4. DAW.b Instruction PSV — 5. Operations CPU Nested DO 6. Loops Flash RTSP 7. Memory Data Y Data 8. Memory Space Interrupt Traps 9 ...
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... MIPS should ensure that the V remains within volts. DD Addresses in the range 0x6000 through 0xFFFF may not be code-protected for this revision of dsPIC30F6011 and dsPIC30F6013 silicon. The 4x PLL mode of operation may not function correctly for certain input frequencies. An interrupt occurring immediately after modifying the CPU IPL, interrupt IPL, interrupt enable or interrupt flag may cause an address error trap ...
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... TABLE 2: SILICON ISSUE SUMMARY (CONTINUED) Item Module Feature Number Interrupt IPC2 Write 35. Controller Sequence Program RTSP 36. Memory Operations ADC Sequential 37. Sampling QEI Index Pulse 38. Mode PWM Time Base 39. Prescalers PWM Output 40. Override CPU I Sleep 41. PD Current ADC Current 42. Consumption in Sleep ...
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... © 2010 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 3. Module: CPU Sequential MAC class instructions, which prefetch data from Y data space using +4 address modification, will cause an address error trap. The trap occurs only when all of the following conditions are true: 1. Two sequential MAC class instructions (or a MAC class instruction executed in a REPEAT or DO loop) that prefetch from Y data space ...
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... Module: CPU The Decimal Adjust instruction, DAW.b, may improperly clear the Carry bit, C (SR<0>), when executed. Work around Check the state of the Carry bit prior to executing the DAW.b instruction. If the Carry bit is set, set the Carry bit again after executing the DAW.b instruction ...
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... Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 These instructions are identified in Table 3. Example 2 demonstrates a scenario where this occurs. Also, always use Work around 2 if the C compiler is used to generate code for dsPIC30F6011/6012/ 6013/6014 devices. (2) Examples of Incorrect Operation ADDC W0, [W1++], W2 ; SUBB.b W0, [++W1 SUBBR.b W0, [++W1 ...
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... Module: CPU When using two DO loops in a nested fashion, terminating the inner-level DO loop by setting the EDT bit (CORCON<11>) will produce unexpected results. Specifically, the device may continue executing code within the outer DO loop forever. This erratum does not affect the operation of the MPLAB C30 compiler ...
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... Affected Silicon Revisions © 2010 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 9. Module: Interrupt Controller Catastrophic accumulator overflow traps are enabled as follows: - COVTE (INTCON1<8> SATA/SATB (CORCON <7:6> carry generated out of bit 39 in the accumulator causes a catastrophic overflow of the accumulator since the sign bit has been destroyed math ...
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... Module: CPU When interrupt nesting is enabled (or NSTDIS bit (INTCON1<15>) is ‘0’), the following sequence of events will lead to an address error trap: 1. REPEAT loop is active interrupt is generated during the execution of the REPEAT loop. 3. The CPU executes the Interrupt Service Routine (ISR) of the source causing the interrupt ...
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... © 2010 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 14. Module: ADC Input channel scanning allows the ADC to acquire and convert signals on a selected set of “MUX A” input pins in sequence. This function is controlled by the CSCNA bit (ADCON2<10>) and the ADCSSL SFR. The ALTS bit (ADCON2<0>), when set, allows the ADC to alternately acquire and convert a “ ...
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... Module: DCI The Data Converter Interface (DCI) module does not function correctly in Slave mode when the following conditions are true: • The DCI module is configured to transmit/receive one serial clock (bit clock) after the frame synchronization pulse, DJST (DCICON1<5> • The frame length chosen is longer than 1 word, COFSG< ...
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... C1RXF0SIDL first SFR read mov C1RXF0SIDL second SFR read © 2010 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 Work around 2: For C Language Source Code For C programmers, the MPLAB C30 v1.20.02 toolsuite provides a built-in function that may be incorporated in the application source code. This function may be used to read any CAN module SFRs. Some examples of usage are shown in the “ ...
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... Note: Applications that use the CAN peripherals and data EEPROM should also refer to module 1. (Data EEPROM) and module 17. (CAN). 20. Module: Flash Memory Addresses in the range, 0x6000 through 0xFFFF, may not be code-protected for this revision of dsPIC30F6011 and dsPIC30F6013 silicon. Work around None. Affected Silicon Revisions A3 ...
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... SET_AND_SAVE_CPU_IPL (save_to RESTORE_CPU_IPL (save_to) © 2010 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 Work around 2: For C Language Source Code For applications using the C language, MPLAB C30 versions 1.32 and higher provide several generic term macros for modifying the CPU IPL. The ...
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... For modification of the Interrupt 1 setting, the INTERRUPT_PROTECT macro can be used. This macro disables interrupts before executing the desired expression, as Example 16. This macro is not distributed with the compiler. EXAMPLE 16: USING INTERRUPT_PROTECT MACRO #define INTERRUPT_PROTECT ( int save_sr; \ SET_AND_SAVE_CPU_IPL (save_sr, 7);\ x; \ RESTORE_CPU_IPL (save_sr); } (void) 0; ...
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... NOP .endr ; Place SLEEP instruction in the last word of program memory PWRSAV #0 © 2010 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 This can be accomplished by replacing all occurrences of the PWRSAV #0 instruction with a function call to a suitably aligned subroutine. The address( ) attribute provided by the MPLAB ASM30 assembler can be utilized to correctly align the instructions in the subroutine ...
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... Work around 2: Instead of executing a PWRSAV #0 instruction to put the device into Sleep mode, perform a clock switch to the 512 kHz Low-Power RC (LPRC) Oscillator with a 64:1 postscaler mode. This enables the device to operate at 0.002 MIPS, thereby significantly reducing consumption of the device. Similarly, instead of ...
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... Clear the I C receiver interrupt flag SI2CF back to step 1 to continue receiving incoming data bytes. © 2010 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 Work around 2: Use this work around for applications in which the receiver interrupt is required. Assuming that the RBF and the I2COV flags in the I2CSTAT ...
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... Module: I/O If the user application enables the auto-baud feature in the UART module, the I/O pin multiplexed with the IC1 (Input Capture) pin cannot be used as a digital input. However, the external interrupt function (INT1) can be used. Work around None. Affected Silicon Revisions ...
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... None. Affected Silicon Revisions © 2010 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 33. Module: I When the I I2CEN bit in the I2CCON register, the dsPIC DSC device generates a glitch on the SDA and SCL pins. This glitch falsely indicates “Communication Start” to all devices on the I with the a bus collision in a multi-master configuration ...
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... Module: CAN CAN Receive filters 3, 4 and 5 may not work for a given combination of instruction cycle speed and CAN bit time quanta. Work around Do not use CAN RX filters 3, 4 and 5. Instead, use filters 0, 1 and 2. Affected Silicon Revisions 35. Module: Interrupt Controller ...
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... Results are shown here for the PWM1H and PWM1L pins only. Similar results will be observed for any other pair of complementary output pins (PWM2H/L, PWM3H/L and PWM4H/L) and any other chosen duty cycle. © 2010 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 40. Module: PWM The output override function of the PWM module, controlled by the OVDCON register and the OSYNC bit (PWMCON2< ...
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... Module: CPU of approximately 100 μA. The device exhibits I PD Work around If the application does not use the on-chip A/D converter possible to reduce the I below 0.1 μA. The following additional measures need to be taken in these circumstances the application hardware, the V (pin 24) on the dsPIC30F601X device should be connected to the circuit ground (GND) ...
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... Symbol Characteristic No. V Input Low Voltage IL DI19 SDA, SCL V Input High Voltage IH DI29 SDA, SCL © 2010 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 specifica- IL Standard Operating Conditions: 3.3V and 5.0V (±10%) (unless otherwise stated) Operating temperature Min Typ Max V — 0.8 SS 2.1 — ...
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... This document replaces the following errata documents: • DS80176, “dsPIC30F6011/6012/6013/6014 Rev. A3 Silicon Errata” • DS80183, “dsPIC30F6011/6012/6013/6014 Rev. B1 Silicon Errata” • DS80198, “dsPIC30F6011/6012/6013/6014 Rev. B2 Silicon Errata” Rev B Document (7/2009) Updated silicon issue 22 (Interrupt Controller). Added Affected Revisions table to issue 41 (CPU). ...
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... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-6578-300 Fax: 886-3-6578-370 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 © 2010 Microchip Technology Inc. 01/05/10 ...